Overview of the impact of downscaling technology on 1/f noise in p-MOSFETs to 90 nm : Noise in Devices and Circuits
Résumé
An overview of theoretical 1/f noise models is given. Analytical expressions showing the device geometry and bias dependencies of 1/f noise in all conduction regimes are summarised. Novel experimental studies on 1/f noise in MOS transistors are presented with special emphasis on p-channel transistors from 90 nm CMOS technology. In addition to the noise in the drain terminal, the gate current noise is investigated because the gate insulator is very thin and significant gate leakage current appears at high gate biases. In the subthreshold regime, the drain current noise agrees with the AN model, whereas in strong inversion the evolutions of the noise level can be described by Hooge's empirical relation. The gate current noise shows 1/f and white noise components. The white noise is very close to shot noise and the 1/f noise component is almost a quadratic function of the gate leakage current. Coherence measurements reveal that the increase of drain noise at high gate biases can be attributed to tunnelling effects in the gate insulator. Both the input-referred (gate) noise and the slow oxide trap density can be used as a figure of merit of the low-frequency noise in MOSFETs.
Mots clés
Waveform
Experimental result
Electrical characteristic
Figure of merit
Tunnel effect
Quadratic function
Shot noise
White noise
Empirical relation
Leakage current
Noise level
Gate current
Transistor drain
MOS transistor
Experimental study
Geometrical factor
Analytical method
Theoretical model
Review
Nanometer scale
1/f noise
p channel
MOSFET