The next generation of mobile terminals is faced with the emergence of the software-defined radio (SDR) concept. The communication devices tend to provide various wireless services through a multi-functional, multi-mode and multi-standard terminal. The SDR concept aims at designing a re-configurable radio architecture accepting all cellular or noncellular standards working in the 0–5-GHz frequency range. Some technical challenges have to be solved in order to address this concept. Working in the digital domain may be a solution but the analog-to-digital conversion cannot be done at Radio Frequencies, at an acceptable resolution and at an acceptable level of power consumption. The idea proposed here was to interface an analog pre-processing circuit between the antenna and a digital signal processor to pre-condition the RF signal. It uses the principle of a fast Fourier transform to carry out basic functions with high accuracy in a low-cost technology like CMOS. This paper presents the design and the behavioral simulations of this analog discrete-time device which gives the hardware flexibility required for a cognitive radio component.