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Chapitre D'ouvrage Année : 2007

Defects Tolerant Logic Gates for Unreliable Future Nanotechnologies

Résumé

In future nanotechnologies failure densities are predicted to be several orders of magnitude higher than in current CMOS technologies. For such failure densities existing fault tolerance implementations are inadequate. This work presents several principles of building multiple-fault tolerant memory cells and logic gates for circuits affected by high defect densities as well as a first evaluation of the area cost and performance.

Dates et versions

hal-00229300 , version 1 (31-01-2008)

Identifiants

Citer

Lorena Anghel, M. Nicolaidis. Defects Tolerant Logic Gates for Unreliable Future Nanotechnologies. Computational and Ambient Intelligence, Springer, pp.422-429, 2007, ISBN :978-3-540-73006-4, ⟨10.1007/978-3-540-73007-1_52⟩. ⟨hal-00229300⟩

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