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Article Dans Une Revue Journal of Electronic Testing: : Theory and Applications Année : 2007

A Case Study on Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis

Résumé

This paper reports a case study on the automatic layout generation and transient fault injection analysis of a Phase-Locked Loop (PLL). A script methodology was used to generate the layout based on transistor level specifications. Experiences were performed in the PLL in order to evaluate the sensibility against transient faults. The circuit was generated using the STMicroelectronics HCMOS8D process (0.18 μm). Results reveal the PLL sensitive points allowing the study and development of techniques to protect this circuit against transient faults.

Dates et versions

hal-00226434 , version 1 (30-01-2008)

Identifiants

Citer

C. Lazzari, Lorena Anghel, Ricardo Reis. A Case Study on Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis. Journal of Electronic Testing: : Theory and Applications, 2007, 23 (6), pp.625-633. ⟨10.1007/s10836-007-5055-x⟩. ⟨hal-00226434⟩

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