A Heavy-Ion Tolerant Clock and Data Recovery Circuit for Satellite Embedded High-Speed Data Links
Résumé
A Clock and Data Recovery (CDR) circuit dedicated to satellite embedded high-speed data links is implemented in a 0.13 µm CMOS technology. Its radiation hardening is obtained thanks to an innovative architecture based on an Injection-Locked Oscillator (ILO) associated with a phase-alignment circuit. Its low Single-Event Transient (SET) sensitivity is shown thanks to heavy-ion and laser testing.