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Communication Dans Un Congrès Année : 2005

A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms

M. D. Galanis
  • Fonction : Auteur
A. Milidonis
  • Fonction : Auteur
G. Theodoridis
  • Fonction : Auteur
D. Soudris
  • Fonction : Auteur
C. E. Goutis
  • Fonction : Auteur

Résumé

In this paper, we propose a methodology for partitioning and mapping computational intensive applications in reconfigurable hardware blocks of different granularity. A generic hybrid reconfigurable architecture is considered so as the methodology can be applicable to a large number of heterogeneous reconfigurable platforms. The methodology mainly consists of two stages, the analysis and the mapping of the application onto fine and coarse-grain hardware resources. A prototype framework consisting of analysis, partitioning and mapping tools has been also developed. For the coarse-grain reconfigurable hardware, we use our previous-developed high-performance coarse-grain data-path. In this work, the methodology is validated using two real-world applications, an OFDM transmitter and a JPEG encoder. In the case of the OFDM transmitter, a maximum clock cycles decrease of 82% relative to the ones in an all fine-grain mapping solution is achieved. The corresponding performance improvement for the JPEG is 43%.
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Dates et versions

hal-00181857 , version 1 (24-10-2007)

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M. D. Galanis, A. Milidonis, G. Theodoridis, D. Soudris, C. E. Goutis. A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms. DATE'05, Mar 2005, Munich, Germany. pp.247-252. ⟨hal-00181857⟩

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