In this paper we propose a methodology for analog design reuse during technology scaling. This method is based on resizing rules resulting in the application of a MOS transistor model. The aims of this scaling are the conservation of the performances of the original circuit and the reduction of power consumption and area. This resizing methodology has been applied on different analog circuits. The original circuit has been designed in 0.8 μm AMS technology with a supply voltage of 5 V and then scaled in 0.35 μm AMS technology with a 3.3 V supply voltage. Finally, the methodology is validated by simulation results.