Multimedia applications such as video and image processing are computation intensive applications. For these applications the bit-width of data and operations is different all over the application. Generating optimized architectures is not an obvious task since it requires a deep bit-width analysis in order to properly size hardware resources. Furthermore implementing several application profiles onto the same chip makes it possible to avoid over-sized architectures or chip reconfiguration. In this paper we propose a design methodology based on high-level synthesis which takes into account multiple bit-width standards in order to generate area and power optimized architectures for embedded devices. First results demonstrate the interest of the approach.