Multimedia applications are characterized by a large number of data accesses (i.e. RAM accesses). In many digital signal-processing applications, the array access patterns are regular and periodic. Optimized Pipelined Memory Access Controllers can be generated. The computational complexity reduction of algorithms, for instance in multidimensional signal processing applications, can be achieved by using execution hazards (conditional statements). In this paper we propose a behavioral synthesis design flow based for data-dominated systems under timing constraints handling both predictable and unpredictable memory access patterns in a memory sequencer. We also analyze the benefits of balancing dynamic address computations from datapath to specialized computation units placed in the memory sequencer thus optimizing area, latency, data locality i.e. reducing the power consumption.