Simulation of assembly generated constraints during SMT processing and size optimisation of the capacitors by design of experiments - Archive ouverte HAL Accéder directement au contenu
Article Dans Une Revue HYBRID CIRCUITS Année : 1993

Simulation of assembly generated constraints during SMT processing and size optimisation of the capacitors by design of experiments

Fichier non déposé

Dates et versions

hal-00164908 , version 1 (24-07-2007)

Identifiants

  • HAL Id : hal-00164908 , version 1

Citer

Y. Ousten, L. Bechou, N. Xiong. Simulation of assembly generated constraints during SMT processing and size optimisation of the capacitors by design of experiments. HYBRID CIRCUITS, 1993, 32, pp. 26-32. ⟨hal-00164908⟩
48 Consultations
0 Téléchargements

Partager

Gmail Facebook X LinkedIn More