CNTFET-based logic gates and simulation
Résumé
This paper deals with the analysis of several logic gates (inverter, NAND, NOR) based on carbon nanotube transistors. By using available compact models we have simulated and analyzed the impact of diameter and contact resistance variations on the transfer characteristics. An interesting conclusion is that CMOS-like gates with non-homogeneous diameters may show better characteristics in comparison with homogeneous diameter ones. Our work represents a first step towards parametric faults modeling for logic circuits based on CNTFET.