Article Dans Une Revue Solid-State Electronics Année : 2002

Low Schottky barrier source/drain for advanced MOS architecture : device design and material consideration

Résumé

An alternative MOSFET architecture based on the use of low barrier Schottky source/drain (S/D) contacts coupled to a thin silicon-on-insulator (SOI) film is described. Two-dimensional device simulations are used to demonstrate the advantage of low Schottky barrier S/D over conventional implanted technologies in terms of current drive capabilities. It is shown that the silicide penetration in the silicon does not increase the contact resistance for this structure while a severe degradation of the current drive is observed for conventional MOS architectures. Experiments conducted on Pt/Ge metallic stacks on p-type silicon show that very low Schottky barriers to hole can be obtained (∼50 meV).

Domaines

Fichier principal
Vignette du fichier
2002-Dubois-SSE-Low-SB-MOS-hal.pdf (313.02 Ko) Télécharger le fichier
Origine Fichiers produits par l'(les) auteur(s)
Licence

Dates et versions

hal-00148735 , version 1 (20-09-2024)

Licence

Identifiants

Citer

Emmanuel Dubois, G. Larrieu. Low Schottky barrier source/drain for advanced MOS architecture : device design and material consideration. Solid-State Electronics, 2002, 46 (7), pp.997-1004. ⟨10.1016/S0038-1101(02)00033-3⟩. ⟨hal-00148735⟩
138 Consultations
153 Téléchargements

Altmetric

Partager

  • More