A high dynamic range CMOS image sensor with on-chip FPN reduction method
Résumé
A high dynamic range CMOS image sensor implementing an innovative fixed pattern noise (FPN) reduction method is presented. The high dynamic range is reach through a logarithmic architecture pixel. An on-chip calibration method is implemented to reduce the FPN caused by process variations, weakness of this architecture. The basic principle is the calibration of each pixel against an in-pixel reference current in place of the diode photocurrent. Two pixel levels corresponding to the photocurrent and a known reference current become available for every pixel. Then a double sampling technique allows to remove offsets due to threshold voltage variations. An innovation of this work consists in the implementation of the current calibration source inside the pixel, allowing a better current precision and a lower power consumption. This FPN reduction method is performed while keeping only four transistors per pixel. A 128x128 pixels test chip has been designed and fabricated in 0.35µm, 3.3V CMOS standard technology. Pixel measures 10x10.6µm² with a fill factor of 33%. The dynamic range expected is up to 120dB with a frame rate up to 30 images per second and a FPN of 2.65%rms of the total dynamic range.