Building and Using System, Algorithmic, and Architectural Power and Energy Models in the FPGA Design-Flow
Résumé
FPGA circuits offer great advantages compared to ASIC or programmable processors. They are often used in complement of such circuits in complex systems. To reduce the time-to-market, the designer needs help for exploring the design space while implementing applications on FPGA. In this paper, we present a complete methodology to perform highlevel estimation and optimization of the power and energy consumptions of applications to be implemented on FPGA circuits. We show how to build and use the necessary power models, at the system level, algorithmic level and architectural level. The development of several power models is presented for different applications, circuits, and at different levels in the design flow. The precision of our models was evaluated in comparison to physical power consumption measurements. Our approach proves relatively accurate for the average error is between 4% and 20% depending on the considered abstration level. We finaly show how to use our methodology to the design space exploration of a FFT application.