This paper presents our contribution in terms of synchronization processor to a SoC design methodology based on the theory of the latency in-sensitive systems (LIS) of Carloni et al.. This methodology 1) promotes pre-developed IPs intensive reuse, 2) segments inter-IPs interconnects with relay stations to break critical paths and 3) brings robustness to data stream irregu-larities to IPs by encapsulation into a synchronization wrapper. Our contribu-tion consists in IP encapsulation into a new wrapper model containing a syn-chronization processor which speed and area are optimized and synthetizability guarantied. The main benefit of our approach is to preserve the local IP per-formances when encapsulating them. This approach is part of the RNRT ALIPTA project which targets design automation of intensive digital signal processing systems with GAUT [1], a high-level synthesis tool.