Highly wireable multilevel synthesis with compiled cells
Résumé
An original method for optimized multilevel synthesis of CMOS circuitry in terms of compiled cells is presented here. A compiled cell is the implementation on silicon of a `lexicographical' factorized Boolean expression. It is recalled how a compiled cell is obtained automatically from the Boolean expression. The rewriting of Boolean functions in terms of compiled cells is then addressed. This leads to a dense and regular layout by abutment of compiled cells. The wiring channels are so suppressed.