Hardware for computing modular multiplication algorithm
Résumé
This paper examines the characteristics of an alternative architecture for computing a modular multiplication based on Montgomery's algorithm, useful in performing RSA public key cryptosystems operations. An experimental 12*12 bits modular multiplier prototype has been designed with this architecture and fabricated by AMS using 0.6 mu m CMOS technology. The architecture, its operation and some simulation results are presented. The evaluation is provided according to the functionality. The active area size is 1.33*0.93 mm/sup 2/, containing about 4100 transistors.