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Communication Dans Un Congrès Année : 2005

A 120nm low power asynchronous ADC

Résumé

This paper discusses the development of a new kind of low power processing chain which dynamically adapts sampling frequency to signals. Thus, the design of an Asynchronous Analog-to-Digital Converter (A-ADC) is tackled. Its principle is based on a non-uniform sampling scheme and asynchronous technology, that allow significant activity and power savings. A test chip targetting 10-bit speech applications has been fabricated using the 120nm CMOS process from STMicroelectronics. The power consumption is lower than 180µW leading to a Figure of Merit two times better than those of classical Nyquist converters recently published.
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Dates et versions

hal-00012718 , version 1 (27-10-2005)

Identifiants

  • HAL Id : hal-00012718 , version 1

Citer

E. Allier, Marc Renaudin, G. Sicard, J. Goulier, A. Dezzani, et al.. A 120nm low power asynchronous ADC. Low Power Electronics and Design, 2005. ISLPED '05. Proceedings of the 2005 International Symposium on, 2005, San Diego, CA, United States. pp.60-65. ⟨hal-00012718⟩

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