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Communication Dans Un Congrès Année : 2001

Modeling and design of asynchronous priority arbiters for on-chip communication systems

Résumé

This paper addresses the design of complex arbitration modules, like those required in SoC communication systems. Clock-less, delay-insensitive arbiters are studied in the perspective of making easier and more practical the design of future GALS or GALA SoCs. The paper focuses on high-level modeling and delay-insensitive implementations of fixed and dynamic priority arbiter. Pre-layout simulations show that arbiters which are able to process several hundreds mega requests per second can be designed using the 0.18 mu m CMOS process of STMicroelectronics.
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Dates et versions

hal-00009605 , version 1 (06-10-2005)

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Paternité - Pas d'utilisation commerciale

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  • HAL Id : hal-00009605 , version 1

Citer

Laurent Fesquet, Marc Renaudin, Jean-Baptiste Rigaud, J. Quartana. Modeling and design of asynchronous priority arbiters for on-chip communication systems. IFIP International Conference On Very Large Scale Integration (VLSI-SOC'01), Dec 2001, Montpellier, France. pp.313-324. ⟨hal-00009605⟩

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