Investigating the effect of approximate multipliers on the resilience of a systolic array DNN accelerator - Institut des nanotechnologies de Lyon
Communication Dans Un Congrès Année : 2023

Investigating the effect of approximate multipliers on the resilience of a systolic array DNN accelerator

Résumé

Deep Neural Networks (DNNs) are nowadays extremely popular in different fields of edge and mobile real-time applications such as surveillance, autonomous systems, etc… Energy efficiency and performance are crucial is such context and, for this reason, several DNN hardware accelerators have been designed using Approximate Computing (AxC) techniques. However, other than efficiency, real-time applications used in safety-critical systems (e.g., autonomous car) require a given level of resilience to hardware faults. Indeed, in the literature, many works discussed so far how to assess the resilience of a given hardware accelerator and how to harden it through the insertion of fault-tolerant mechanisms. Fault tolerance is usually achieved by using redundancy that costs in terms of area, power consumption and latency. For the case of DNNs, the redundancy is selectively applied to reduce its cost and protect only the "critical" components. This work aims at proposing a novel approach entirely based on the use of AxC to increase the resilience of DNNs without using redundancy and thus avoiding extra costs. In particular, we studied the impact of AxC multipliers on a systolic array architecture used to accelerate the DNN execution. Preliminary results show that by using an AxC multiplier, it is possible to improve the resilience of almost 10% with better efficiency than the "precise" implementation.
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Dates et versions

hal-04674779 , version 1 (21-08-2024)

Identifiants

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Salvatore Pappalardo, Ali Piri, Annachiara Ruospo, Ian O'Connor, Bastien Deveautour, et al.. Investigating the effect of approximate multipliers on the resilience of a systolic array DNN accelerator. 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2023), Oct 2023, Juan-Les-Pins, France. ⟨10.1109/DFT59622.2023.10313535⟩. ⟨hal-04674779⟩
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