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            <title xml:lang="en">Hardware security of embedded processors against fault injection attacks</title>
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                <title xml:lang="en">Hardware security of embedded processors against fault injection attacks</title>
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                <authority type="supervisor">Guy Gogniat</authority>
                <authority type="supervisor">Vianney Lapôtre</authority>
                <authority type="jury">Vincent Beroulle [Président]</authority>
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                <term xml:lang="en">Fault injection attacks</term>
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                <term xml:lang="en">Hardware cybersecurity</term>
                <term xml:lang="fr">Processeur embarqué</term>
                <term xml:lang="fr">Attaques par injection de fautes</term>
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              <p>Embedded processors can be subject to physical attacks due to some proximity between an attacker and the circuit. Fault injection attacks (FIAs) exploit perturbations in the circuit to reveal secret data or bypass security features. Various protection methods exist against FIA: error code correction/detection, functional property check, redundancy, randomization, etc. In software, instruction duplication and triplication are easy to use to secure critical codes but lead to important overheads in execution time and code size. More, software protections rarely take into account hardware implementation details, such as the processor pipeline, and may not be as effective as intended. We propose a hardware support for instructions replay in a basic RISC processor. It consists in a small extension of the instruction set (one new instruction), a few detection and vote elements (mainly registers and comparators) and light modifications of the processor control. We explore various configurations of internal protection elements for hardware replay. The core area overhead is about +30% while the clock frequency is reduced by less than 10% on FPGA. The hardware replay allows to significantly reduce the execution time and code size compared to a pure software replay protection.</p>
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              <p>Les processeurs embarqués peuvent faire l’objet d’attaques physiques en raison de la proximité entre l’attaquant et le circuit. Les attaques par injection de fautes (FIA) exploitent des perturbations du circuit pour révéler des données secrètes ou contourner des dispositifs de sécurité. Il existe plusieurs méthodes de protection contre les FIA : correction/détection d’erreurs, vérification des propriétés fonctionnelles, redondance, randomisation, etc. En logiciel, la duplication et la triplication d’instructions sont faciles à utiliser pour sécuriser des codes critiques mais entraînent des surcoûts importants en temps d’exécution et taille de code. De plus, les protections logicielles prennent rarement en compte les détails d’implémentation du matériel, comme le pipeline du processeur, et peuvent ne pas être aussi efficaces que prévu. Nous proposons un support matériel pour le rejeu d’instructions dans un processeur RISC élémentaire. Il consiste en une petite extension du jeu d’instructions (une nouvelle instruction), quelques éléments de détection et de vote (principalement des registres et des comparateurs) et de légères modifications du contrôle du processeur. Nous explorons différentes configurations d’éléments de protection internes pour le rejeu matériel. Le surcoût en surface du cœur est de 30% et la baisse de fréquence d’horloge de 10% sur FPGA. Le rejeu matériel réduit de manière significative le temps d’exécution et la taille du code par rapport à une protection purement logicielle.</p>
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