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              <p>In the context where the traditional CMOS technology approaches its limits, some nanowire-based fabric proposals emerged, which all exhibit some common key characteristics. Among these, their bottom-up fabrication process leads to a regularity of assembly, which means the end of custom-made computational fabrics in favor of regular structures. Hence, research activities in this area, focus on structures conceptually similar to today’s reconfigurable PLA and/or FPGA architectures. A number of different fabrics and architectures are currently under investigation, e. g.CMOL, FPNI, NASIC. These proof-of-concept architectures take into account some fabrication constraints and support fault tolerance techniques. What is still missing is the ability to capitalize on these experiments while offering a one-stop shopping point for further research, especially at the physical-design level of the circuit design tool-flow. Sharing metrics, tools, and exploration capabilities is the next challenge to the nano-computingcommunity.We address this problem by proposing a model-driven physical-design toolkit based on the factorization of common domain-specific concepts and the reification of the tool-flow. We used this tool-flow to drive the design-space exploration in the context of a novel nanoscale architecture, and we showed that such an approach assures design convergence based on frequent quantitative evaluations, moreover it enables incremental evolution of the architecture and the automation flow.</p>
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              <p>Actuellement, comme la technologie CMOS arrive à ses limites, plusieurs alternatives architecturales nanométriques sont étudiées. Ces architectures partagent des caractéristiques communes, comme par exemple la régularité d’assemblage, qui contraint le placement de dispositifs physiques à des motifs réguliers. Par conséquence, les activités de recherche dans ce domaine sont focalisées autour des structures régulièressimilaires, d’un point de vue conceptuel, aux architectures réconfigurables de type PLA et FPGA. Parmi ces différents travaux, ont peut citer CMOL, FPNI, NASIC. Ces prototypes architecturaux sont conçus pour répondre à des contraintes de fabrication et incluent des politiques detolérance aux défauts. Par contre, il manque la possibilité d’exploiter ces expériences et d’offrir une solution qui, en capitalisant les résultats obtenus, puisse offrir une infrastructure unique pour les futurs recherches dans ce domaine. Ceci est vrai surtout au niveau du flot de conception physique ciblant l’automatisation du processus de création de circuit. Le partage de métriques, outils et supports d’exploration est le futur défi de la communauté nano-électronique.On répond à ce problème en proposant un flot de conception physique, reposant sur une méthodologie de développement dirigé par les modèles, qui factorise les concepts métiers et réifie les éléments du flot de conception. Nous avons utilisé ce flot pour explorer l’espace de conception d’une nouvelle architecture nano-métrique et on a montré qu’une telle démarche permet la convergence du processus de conception à l’aide de fréquentes évaluations quantitatives. De plus, cette méthodologie permet l’évolution incrémentielle de l’architecture et du flot de conception.</p>
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