\newpage
\chapter{Unconventional digital computing approach: memristive nanodevice platform}
\label{imp-crossbar}
\begin{abstract}
 Memristor is a two-terminal nanodevice that has recently
attracted the attention of many researchers. Its simple
structure, non-volatility behavior, high-density integration, 
and low-power consumption make the memristor a
promising candidate to act as a switch in digital gates
for future high-performance and low-power nanocomputing applications. 
In this chapter, we model the behavior
of memristor by using Verilog-A tools. To investigate its 
characteristics in a circuit, we use the HSPICE simulator.
Furthermore, a library of digital gates is provided by
using two approaches to make digital gates: the first one
is based on material implication (IMP) and the second
one is based on crossbar arrays. Finally, we 
compare and evaluate both computation methods.
\end{abstract}

\section{Introduction}
It is important to be able to
control the states of the conductance of memristor 
in order to use memristors for computing in general, analog or digital.
As the memristor is applied in the different platform as a two terminal 
device for state modification new approaches are required.
In traditional CMOS computing, using transistor state
we can switch between `0' and `1' to be able to 
produce Boolean functions such as NOT, AND, OR and etc. 
In CMOS-based computing, the switching of the transistor is controlled 
by a third terminal, (Base in BJT and Gate in MOSFET).
The story of the state controlling for memristor nanodevice is 
different as there are only input and output terminals (no terminal for 
controlling the states of the switch). Therefore, the new methods
and approaches are studied 
to be able to use two-terminal devices for computing. 

In this chapter, we study and discuss two methods for digital computing
by memristive tow-terminal devices mainly based on our publication
\cite {shahsavari_unconventional_2015}. There are two main approaches, namely 
 \textit{material implication} (IMP) or stateful logic and \textit{programmable crossbar architecture}
 that are discussed in this chapter. Material implication
 was studied by Whitehead and Russell in early 1900s in \textit {Principia
Mathematica} \cite{principa_1927}. IMP can be implemented on memristor with couple of sequences of control voltages.
In this study based on previous research works on IMP, we establish a functionally complete Boolean operation 
to be able to build other standard logic gates. The second method,
combination of memristor with crossbar interconnect technology, 
 has been demonstrated as
offering the potential of creating configurable electronic devices with applications in digital computation, signal processing and artificial
intelligence \cite{crossbar}. In this chapter, we analyze the application of crossbar array architecture in 
constructing logic building blocks. Our contribution is to present a comprehensive 
 library to build a complete set of Boolean gates using both approaches. At the end of this chapter 
we evaluate and compare both methods. 
 

The logic computing applications of memristor have been investigated by several 
researchers \cite{Leveraging,LehtonenPL12,Crossbar-mem,crossbar,RajaM10,selfprog1,lehtonen_stateful_2009,imp-nature,xie_boolean_2016}.
For instance, Borghetti et al. \cite{imp-nature} 
used \textit{material implication} (IMP) logic 
operation to carry out logic computation by using memristors.
 In IMP approach, $A$ IMP $B$ ($A$$\rightarrow$$B$) operation means `if $A$,
 then $B$' and can be read as $A$ implies $B$. IMP together with a FALSE gate
 are able to form a functionally complete set (any Boolean function can be 
 expressed). By applying memristor as a digital switch, a high memristance
 (memristor resistance) is considered as logic `0' and a low memristance is
 considered as logic `1'. 
Another approach to make gates by a two-terminal device as a switch is the 
\textit{programmable crossbar architecture} \cite{crossbar,Crossbar-mem}. 
The crossbar nanowire array architecture 
can be used to compute logic functions by using memristor 
as a switch between two nanowires \cite{RajaM10}. 

\section{Stateful implication logic}
\label{sec3}
\label{S_IMP}
One of the basic potential applications of memristors is to utilize them 
in building blocks of logic gates.
Therefore, by applying a digital pulse voltage to the memristor
terminals, we have a switch with ON or OFF state.
Unlike conventional CMOS, in memristor-based gates, data
 will be stored as a resistance rather than a voltage. 
In this case, the latches are non-volatile. Thus, $R_{ON}$ displays logic `1' 
which means closed switch
and $R_{OFF}$ displays `0' for presenting open switch. 
In contrast to the three-terminal CMOS-based transistor as a switch, 
in a two-terminal switch, there is no terminal to control ON or OFF 
states of the switch. Consequently,  
instead of conventional Boolean logic, we should find other substitutes 
to create a logic gate.

IMP (Figure \ref{IMPf}.a) is a way to use one memristor to control the other one.
IMP is recognized as a promising method for 
making gates by memristors \cite{LehtonenPL12,lehtonen_stateful_2009, imp-nature,marranghello_factored_2015}. 
In IMP structure, memristors have different roles in different stages of the computing process:
 input, output, computational logic element, and a latch depending upon which write, read, 
 computing and storing processes are taking place, respectively.
 \begin{figure}[tp]
\centering
\includegraphics[scale=0.7]{figures/ch2/IMP1}
\caption{\small{Memristor-based IMP:  \textbf{a)} circuit 
schematic, \textbf{b)} IMP truth table.}}\label{IMPf}
\end{figure}
 
To figure out how IMP operates, imagine $A$ as a question and $B$ as an answer to that question. 
If the question is wrong, any answer (wrong or correct) makes a 
true output (logic 1), as depicted in Figure \ref{IMPf}.b. The only case for the false (logic 0) 
output would be a wrong answer to a correct question. So the implication logic is 
equivalent to function ($\neg$$A$)$\vee$$B$. Figure \ref{IMPf}.a shows the basic circuit of
memristors $A$ and $B$ to perform implication logic, which are formed by
 the vertical nanowire crossing over the
 horizontal nanowire connected to a load resistor $R_{G}$.  After the operation of material 
 implications, the result is stored as the state of switch $B$ ($B'$) 
while $A$ is left unchanged. 

To switch between logic `1' to logic `0' (and vice versa), we need
a tri-state voltage driver with a high impedance output state 
when it is undriven.
$V_{set}$ is a negative voltage which should be applied to its corresponding
tri-state driver. $V_{set}$ can switch memristor to conductive state with low resistance 
$R_{ON}$. Similarly, the positive voltage $V_{clear}$ is required to change
 the memristive switch state to low-conductance (high-resistance) state $R_{OFF}$. It is
 important to mention that the magnitude of $V_{set}$ and $V_{clear}$ must be larger
 than device threshold voltage for switching `ON' and `OFF'. In order to remain in a specific 
 state (line 3 in truth table \ref{IMPf}.b), the $V_{cond}$ is applied as a negative voltage
 with a magnitude smaller than $V_{set}$. Consequently, tri-state drive ---since is not in 
 high-impedance state--- is pulsed by one of the $V_{set}$, $V_{clear}$ or $V_{cond}$.
By applying $V_{cond}$ and $V_{set}$ to $A$ and $B$ simultaneously, the memristive IMP 
operates properly. Although the conditional voltage ($V_{cond}$) is not
 necessary, except for the 
case $A$$B$=`10' (third line in the truth table Figure \ref{IMPf}.b), it is possible to 
either apply $V_{cond}$ or use high-impedance (HZ) for all other cases. If $V_{set}$ is applied to
 $B$ alone,
 it would be unconditionally 
logic `1', nevertheless applying $V_{cond}$ by itself to $A$ does not change its state. 
On the other hand, if both voltages are applied together, the present state of 
switch $A$ determines the next state of switch $B$. If $A$=`0', it means memristor $A$ 
is in high resistance state ($R_{OFF}$). Therefore, there is a small voltage drop across $R_{G}$. 
In this case, $B$ will be set and $A$ is left unchanged. Alternatively, if present state 
of $A$=`1', switch $A$ is in low resistance state and $V_{cond}$ drops across $R_{G}$, 
so both $A$ and $B$ remain unchanged. It should be noted that the $R_{G}$ value must
 be chosen such that
  $R_{ON}$$<$$R_{G}$$<$$R_{OFF}$, where $R_{ON}$ and $R_{OFF}$ are resistance states of 
  `ON' and `OFF' switches, respectively.
  
  \begin{figure}[h]
\centering
\includegraphics[width=8cm]{figures/ch2/NAND_IMP.pdf}
\caption{\small{NAND configuration with IMP: \textbf{a)} circuit schematic, \textbf{b)} 
required voltages for controlling the process, \textbf{c)} sequential truth table
 to obtain 
NAND.}}\label{NAND_IMP}
\end{figure}
\subsection{Functionally complete Boolean operations}
In Boolean logic algebra, a set of logic operations is called functionally complete if all 
other logic functions can be constructed from combining the members of this set. 
The single-element sets  \emph{NAND}  (AND, NOT) and  \emph{NOR} (OR, NOT) are functionally 
complete operations. In addition,
it has been demonstrated that all Boolean expressions can then be written in one of the standard
normal forms using only a (IMP) operation and a \emph{false} (Inverse) operation \cite{lehtonen_stateful_2009, imp-nature}.
In fact, to show that the memristive implication logic is a functionally complete operation; 
the easiest way is to synthesize the NAND function with it. 

A circuit with three memristors $A$, $B$, and $C$ is illustrated schematically in Figure 
\ref{NAND_IMP}.a. Assume two implication operations being performed subsequently,
 first $A$ IMP $C$ and then $B$ IMP $C$. Hence $A$ and $B$ are inputs and $C$  is output. 
 The final output result is represented  
with variable C$''$ in Figure \ref{NAND_IMP}.c. Firstly, $V_{clear}$ should be applied to 
switch $C$ to create the \emph{false} operation ($C'=(C$ IMP $0$)). By applying 
$V_{cond}$
 and $V_{set}$  pulses to $A$ and $C$ respectively, the second step would be performed. 
 Finally, $C''=(B$ IMP $C$) is yielded by applying $V_{cond}$ to
 $V_{B}$ and  $V_{set}$ to $V_{C}$ (see Figure \ref{NAND_IMP}.b and Figure \ref{NAND_IMP}.c).
 In other words, the resulting state of switch $C$ can be written as:
 \begin{eqnarray*}
C=B \; \mbox{IMP} \; (A \;  \mbox{IMP} \; C)=\neg{B}\vee ((\neg{A})  \vee  C)
\end{eqnarray*}
  if $C=0$ initially then 
   \begin{eqnarray*}
C&= \neg B \vee ((\neg A) \vee 0)=(\neg B) \vee (\neg A) \nonumber \\
    &=\neg(A\wedge B)
\end{eqnarray*}
which is a NAND operation. Similarly, we can produce equal IMP structure of other 
logic operations. In Table \ref{Tab-1} different Boolean logic gates are listed. 
Obviously, we can demonstrate all logic relations in Table \ref{Tab-1}, not only 
by applying Boolean logic rules 
but also by checking the truth tables of both sides of relations.
\begin{table}[htp]

\caption{\small{Different logic operations made by IMP operations and 
the number of required memristors}}
\label{Tab-1}
\begin{center}
%\rowcolors{1}{brown}{gray}
\scalebox{0.9}{
\begin{tabular}{|p{2.1cm}|p{4.7cm}|c|}

\hline
Logic Operation & Equal IMP functions &\#Device \\
\hline
NOT $A$ &  $A$ IMP $0$ & 3 \\
\hline
$A$ AND $B$ & \{$A$ IMP ($B$ IMP $0$)\} IMP $0$ & 4\\ 
\hline
$A$ NAND $B$ & $A$ IMP ($B$ IMP $0$) & 3\\
\hline
$A$ OR $B$ & ($A$ IMP $0$) IMP $B$ & 3\\
\hline

$A$ NOR $B$ & \{($A$ IMP $0$) IMP $B$\} IMP $0$ & 4\\
\hline
 $A$ XOR $B$&($A$ IMP $B$) IMP \{($B$ IMP $A$) IMP $0$\}& 3\\
 \hline

\end{tabular}
}
\end{center}
\label{tab-1}
\end{table}

\section{Crossbar architecture}
\label{sec4}
Programmable crossbar architectures have been proposed as a
promising approach for future computing architectures because of their
simplicity of fabrication and high density, which support
defect tolerance \cite{crossbar,snider-cross,vourkas_alternative_2016}. In such architectures, assume
that each junction within the crossbar can be utterly 
configured to activate an electronic device, such
as a resistor, diode, transistor, or recently memristor. In fact, 
attractive features of memristor,
 such as simple physical structure, non-volatility, high-density, 
 and unlimited endurance make this nano-device 
one of the best choices to play a switch role in the crossbar junctions. 
The memristive-based crossbar opens new windows to 
explore advanced computer architecture, different from the classical 
Von Neumann architecture \cite{snider-cross}. 
On the other hand, in crossbar architecture, memory and logic operators 
are not separated. The memory can perform logic implementations on the 
same devices which store data. 
This is because during the operation process, control signals determine 
which elements act as logic gates and which ones act as memory cells.
\subsection{Memristive switches in crossbar architectures}
Each junction in a crossbar could be connected or disconnected by replacing 
a memristor as a switch in the junction point between two vertical
and horizontal nanowires as depicted 
in Figure \ref{crosbar-switches}.a. Such a switch is in high 
resistance ($R_{OFF}$) (Figure \ref{crosbar-switches}.c) for open
state or low resistance ($R_{ON}$) (Figure \ref{crosbar-switches}.d)
for close state, similar to the states
 of memristor in Section \ref{S_IMP}. The memristive switch retains 
 its state as long as the voltage drop across it, which is not more than 
 the required threshold voltage to change the memristor state. 
 \begin{figure}[htp]
\centering
\includegraphics{figures/ch2/crosbar-switches.pdf}
\caption{\small{Different states of a switch in a crossbar array.}}\label{crosbar-switches}
\end{figure}
In Figure \ref{crosbar-switches}.a the input voltage ($v_{in}$) either could 
be connected to the output voltage of an external CMOS circuitry or be connected to the output of another 
latch from the previous stage. As we have already mentioned, data in our 
architecture is saved as the resistance of the memristive latch. However, 
for data transferring, an input voltage is necessary. Indeed, this input 
voltage is driven by the state of the input impedance 
($R_{in}$ in Figure \ref{switches-states}), which is a memristive switch. 
This voltage can be disconnected which means the floating state (for instance,
a very high impedance $R_{OFF}$). The floating state input happens when 
the input memristor ($R_{in}$ in Figure \ref{switches-states}.a) is OFF. Subsequently, 
the input voltage can also be a fixed negative voltage ($-V_{f}$) with less magnitude 
than the threshold, while the input memristor ($R_{in}$ in 
Figure \ref{switches-states}.b) is ON.


The memristive switches can be configured as an inverting
or non-inverting mode as it is depicted in Figure \ref{switches-states}.c 
and Figure \ref{switches-states}.d, respectively. If the stored data in 
the receiving switch is the logical complement of the
input data, the configuration is in the inverting mode. If the stored
data is the same as the input data the configuration is in the non-inverting mode. 
 Different control signals make different configurations. 
 Inverting configuration requires three steps to perform the appropriate latch operation:\\
1) We preset the switch unconditionally open (Figure \ref{switches-states}.a) by 
applying a positive voltage (more than the positive threshold) to the control of the vertical nanowire
 and also by forcing input to the high impedance mode.
 A diode is also required to provide a low-impedance path to the ground to protect the junction.\\
2) If the input voltage is logic `1' then $R_{in}$=$R_{ON}$ and $-V_{f}$ drops 
across $R_{G}$, so the voltage across memristor 
is not enough to close it and the switch remains OFF.
 On the other hand, when input is logic `0', then $R_{in}$=$R_{OFF}$ and 
the memristor switch turns ON. Thus, the junction has held the inverted state of the input
(see Figure \ref{switches-states}.b).\\
3) The input signal must be in the high impedance (disconnected). The state of the
switch is read out onto the horizontal nanowire. This is accomplished
  by driving the vertical nanowire with a small voltage whose magnitude is less 
  than the threshold control voltage (can not change the switch state). 
  We call this voltage $v_{R}$ (Read voltage).\\
For non-inverting configuration, as depicted in Figure \ref{switches-states}.d, 
the pull-down resistor $R_{G}$ is not required when writing the state of the driving switch to the 
receiving one. The steps for appropriate latch operation are the same as the 
`inverting configuration' except grounding the vertical nanowire of the 
driving switch rather applying a negative voltage in conditionally close step.
In this case, by applying the negative voltage to the vertical control line, 
the receiving switch will be close if the driving switch is close 
(low-impedance path to the ground) and the receiving switch remains open if the driving switch is open.
Thus, the state of the first switch is replicated in the second switch. 

\begin{figure}[tp]
\centering
\includegraphics[scale=1.2]{figures/ch2/switches-states.pdf}
\caption{\small{Different states and configurations of 
the memristive switches in a crossbar array.}}\label{switches-states}
\end{figure}

\subsection{Configurable crossbar array logic gates}
In this section, we demonstrate how to make a gate by using the crossbar 
approach. We start using crossbar to make a 3-input AND gates. Figure \ref{crossbar-AND}.a shows a
crossbar array which consisting of 8 memristors. We need three inputs A, 
B, and C, each of which is assumed to be impedance encoded. Basically, 
various voltages are applied to vertical
 nanowires to control the memristive switches. The inputs are connected 
 to the horizontal wires as represented in Figure \ref{crossbar-AND}.a. 
 The crossbar array functions as an AND gate by applying the following sequences.
\begin{figure} [ht]
\centering
\includegraphics{figures/ch2/crossbar-AND.pdf}
\caption{\small{The crossbar array architecture for AND function with memristor switches: 
\textbf{a)} by applying the positive voltages all switches become open (clear), \textbf{b)} 
capture data in the input latches,
\textbf{c)} transfer data to the wired-AND switches, \textbf{d)} if all inputs are `1' 
(open) then the X spot is not negative so
the output switch has enough voltage across it to be ON, \textbf{e)} open all wired-AND 
switches to be prepared to read output, 
\textbf{f)} read output.}}\label{crossbar-AND}
\end{figure}
\begin{enumerate}
\item  All junctions are unconditionally opened by applying a positive
voltage higher than the threshold voltage to the $v_{in}$, $v_{and}$, $v_{out}$ control vertical lines.
\item  By driving $v_{in}$ with a negative voltage, 
the input data (A, B, C) are latched in the input switches. The inputs are in the inverting configuration thus `0' and `1' inputs, close and open the switches, respectively (Figure \ref{crossbar-AND}.b). 
\item  In this step, by driving the $v_{in}$ and K
input to the ground, as well as $v_{and}$ to the 
negative voltage (Figure \ref{crossbar-AND}.c) the input data are latched to the wired-AND 
junctions.
\item  In this step, the vertical control lines of
the input and output ($v_{in}$, $v_{out}$) are activated
by a negative voltage to capture the result to the output 
memristor (S8). The voltage in point $X$ in Figure \ref{crossbar-AND}.d 
can determine output switch state. If there is at
least one closed input (also wired-AND) in the route from
$v_{in}$ to the X point, the negative voltage efficacy 
causes the output switch to stay open. The reason is 
that the potential difference across the output switch
is not enough to close it. It is noteworthy to mention 
that the voltage at X point is yielded from the voltages
dividing between the resistance of switches 
 in the route and S7 that connected to the ground in the 
 last horizontal nanowire line.
\item By driving a positive voltage to $v_{and}$, 
all junctions in this column will be opened (Figure \ref{crossbar-AND}.e).
\item The AND of the three inputs is stored in the
output switch and is ready to be read out.
\end{enumerate}
 If the output switch is at inverse mode (inverting configuration),
 the crossbar array becomes a 3-input NAND gate. Moreover, 
the crossbar array can also become a 3-input NOR gate, if $R_{G}$'s
are removed while input data are applied to the circuit 
(Non-inverting configuration). By inverting the last output with
the recent situation of the inputs, the crossbar architecture becomes
a 3-input OR gate. Consequently, all logic gates are created except
XOR and XNOR, which require a little different structures.
First, we create an exclusive-NOR gate, subsequently, by inverting
the output, XOR is obtained. To implement XNOR, two
midterms should be OR'ed together.
 The crossbar array operation for creating XNOR is
similar to AND crossbar array in Figure \ref{crossbar-AND}.
However, three additional steps are required. To simplify the 
crossbar array, we apply two variables $A$ and $B$ (Figure \ref{XOR_cross}).
In the following, we discuss these sequences step by step.
 \begin{enumerate}
\item  All junctions are unconditionally opened by applying a 
positive voltage to the $v_{in}$, two $v_{AND}$'s, and  $v_{out}$ control lines.
\item  By driving $v_{in}$ with a negative voltage, 
the input data ($A$, $B$, $\bar{A}$, $\bar{B}$) are 
latched in the input switches. The inputs are in the
inverting configuration, therefore, `0' and `1'
inputs close and open the switches, respectively. 
\item In this step, by driving the $v_{in}$ and K input 
to the ground, and $v_{AND1}$ to the negative voltage, 
the input data are latched to the wired-AND for the first minterm. 
\item  In this step, the vertical control lines of input
and output ($v_{in}$, $v_{out}$) are activated by a 
negative voltage for first minterm to capture the result ($\bar{A}$$\bar{B}$) 
to the output. 
\item By applying the positive voltage to $v_{AND1}$ (the wired-AND),
junctions become open for the first minterm.
\item For the second minterm implementation, step 3 should be 
repeated by applying a negative voltage to $v_{AND2}$.
\item In this step, the control lines of input and output ($v_{in}$, $v_{out}$)
are activated by a negative voltage for the second minterm to 
capture the result ($AB$) to the output.
It is worth to note that performing OR of the two minterms is 
sequential rather than concurrent. It means that if the output
switch is set into the close state by the first minterm, the
value of the second minterm has no effect. Otherwise, changing 
the state of the output switch is dependent on the second minterm.
\item By applying the positive voltage to the $v_{AND2}$, 
the wired-AND junctions become open for the second minterm.
\item The XNOR of two inputs $A$ and $B$ is stored in the 
output switch and it is ready to be read out.
\end{enumerate} 
It is also possible to make other Boolean logic functions by
applying NAND combinations. However, it requires a larger number of memristive switches. 
Furthermore, it nullifies the most important capability of memristors, i.e. configurability. 
\begin{figure}[htp]
\centering
\includegraphics[width=7cm]{figures/ch2/XOR_cross.pdf}
\caption{\small{Crossbar array architecture for exclusive-NOR function.}}\label{XOR_cross}
\end{figure}

\section{Evaluation} 
\label{sec5}
In this section, we present an evaluation of both the IMP and crossbar array approaches.
Both approaches have significant advantages over the CMOS-based logic gates, such as 
having computation and storing using the same physical unit,
 non-volatility, and small scalability because of the nature of memristive switches. 
 By applying the IMP method, the number of memristors to make a gate can be saved. The less number
of memristive switches causes less power consumption and cost. Table \ref{tab-2} 
provides the number of memristors required to make various logic gates in both cases. 
\begin{table}[ht]
\caption{\small{The number of memristive switches to make logic gates for the 
imp and crossbar array approaches.}}
\begin{center}
%\rowcolors{1}{brown}{gray}
\scalebox{0.9}{

%\begin{tabular}{|p{3cm}|p{2cm}|p{2cm}|}
\begin{tabular}{|l|c|c|}
\hline
Logic Operation & \#IMP & \#Crossbar Array\\
\hline
$S$ $\leftarrow$ NOT $A$ &  2 & 3\\
\hline
$S$ $\leftarrow$ $A$ AND $B$ & 4 & 6\\ 
\hline
$S$ $\leftarrow$ $A$ NAND $B$ & 3 & 6\\
\hline
$S$ $\leftarrow$ $A$ OR $B$ & 6 & 6\\
\hline

$S$ $\leftarrow$ $A$ NOR $B$ & 6  & 6\\
\hline
 $S$ $\leftarrow$ $A$ XOR $B$& 7 & 11\\
 \hline

\end{tabular}
}
\end{center}
\label{tab-2}

\end{table}
We note that the number of memristors to make gates in the IMP approach in Table \ref{tab-1}  
is different from Table \ref{tab-2}. When logic operations listed in Table \ref{tab-1} operate 
on two variables $A$ and $B$, the original logic would be lost during the implication process. For 
instance, in case of NAND, only $B$ is changed and in case of XOR both $A$ and $B$ will change. 
Therefore, to store data we require the additional number of memristive 
switches. For a more detailed explanation see \cite{Arith}.
Despite the overhead introduced in the crossbar approach in terms of number of memristors, 
it can dynamically adapt its logic function by controlling voltages. Therefore, based on the run-time
 requirements, the crossbar array approach is adaptable and reconfigurable.
 \section{Conclusions}
\label{sec6}
In this chapter, based on the electrical model of the memristor is represented in Chapter \ref {ch1}, we show how physical 
properties of this device can be utilized for digital circuit applications.
 Memristor is a two-terminal device, therefore, we need new approaches to apply it to operate as a switch. 
IMP logic with memristor is studied as the first method to create digital gates. We demonstrated that by 
using IMP and the inverse function (NOT),
 it is possible to produce all digital Boolean functions. In the IMP approach,
 the number of memristors to make gates 
are fewer than the crossbar array approach. We proposed the crossbar array 
architecture as the second novel promising technique for nanocomputing binary paradigm. 
The crossbar array method with memristive switches has been investigated comprehensively.
Reconfigurability is the most significant advantage of using the crossbar array 
architecture. It is interesting to note that in both computing techniques,
the storing and computing units are physically the same. 
This property has the potential to overcome the memory bottleneck. 
For future work, one can organize a Programmable Logic Device (PLA) 
platform in such a way that the crossbar array operates as a programmable
AND array beside IMP as a fixed connection for the OR array.
 %For make the switches off (Open), a positive voltage should apply to the $v_{in}$ whi