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222 Results
A system-level overview and comparison of three High-Speed Serial Links: USB 3.0, PCI Express 2.0 and LLI 1.0Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Apr 2013, Karlovy Vary, Czech Republic. pp.147-152
Conference papers
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A General Framework for Average-Case Performance Analysis of Shared ResourcesEuromicro Conference on Digital System Design (DSD'13), Sep 2013, Santander, Spain. pp.78-85, ⟨10.1109/DSD.2013.116⟩
Conference papers
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Disydent : un environnement pour la conception de systèmes numériques synchronesSCS congrès international de Signaux Circuits et Systèmes, Mar 2004, Monastir, Tunisie. pp.72-77
Conference papers
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Scalable High-Performance Architecture for Convolutional Ternary Neural Networks on FPGAField Programmable Logic and Applications (FPL), 2017 27th International Conference on, Sep 2017, Gent, Belgium
Conference papers
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A Deadlock-Free Distributed Routing Algorithm for Vertically Partially Connected 3D-NoCs12th International Forum on Embedded MPSoC and Multicore, Jul 2012, Quebec, Canada
Conference papers
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Formal Analysis of Single Wait VHDL processes for Semantic Based Synthesis12th IEEE International Conference on VLSI Design, Jan 1999, Goa, India. pp.151-156, ⟨10.1109/ICVD.1999.745140⟩
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Deterministic reversible MPSoC debugger based on virtual platform execution tracesDesign Automation for Embedded Systems, 2016, 20 (1), pp.47-63. ⟨10.1007/s10617-015-9167-8⟩
Journal articles
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Effective System Level Simulation Techniques and Cross-Layer Perspectives on Low Power DesignDesign, Automation and Test in Europe (DATE'2018), Mar 2018, Dresden, Germany
Conference papers
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Flexible hardware/software interface modeling using high level service based component modelThe 13th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI'06), April 3-4, 2006, Nagoya, Japan. pp.85-91
Conference papers
hal-00080922v1
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Networks-In-Package: Performances management and design methodologyIEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT'08), Apr 2008, Hsinchu, Taiwan. pp.140-143, ⟨10.1109/VDAT.2008.4542432⟩
Conference papers
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3D Integration for NoC-based SoC ArchitecturesSpringer, pp.278, 2011, ⟨10.1007/978-1-4419-7618-5⟩
Books
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Spidergon STNoC design flowIEEE/ACM International Symposium on Networks on Chip (NoCS'11), May 2011, Pittsburg, Pa., United States. pp.267 - 268
Conference papers
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Multiprocessor System-on-Chip Prototyping Using Dynamic Binary TranslationHandbook of Hardware/Software Codesign, springer, pp.565-591, 2017, 978-94-017-7266-2. ⟨10.1007/978-94-017-7267-9⟩
Book sections
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Teaching basic computer architecture, assembly language programming, and operating system design using RISC-VRISC V week 2019, Oct 2019, Paris, France
Conference papers
hal-02614532v1
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Modular on chip multi processor for routing applicationsEuro-Par 2004 - 10th European Conference on Parallel computing, Aug 2004, Pise, Italy. pp.847-855, ⟨10.1007/978-3-540-27866-5_113⟩
Conference papers
istex
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On cache coherency and memory consistency issues in NoC based shared memory multiprocessor SoC architectures9th EUROMICRO Conference on Digital System Design (DSD'06), Aug 2006, Dubrovnik, Croatia. pp.53-60, ⟨10.1109/DSD.2006.73⟩
Conference papers
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Service Dependency Graph for HW/SW Interfaces Modeling: The Motion-JPEG Case Study7th International Conference on ASIC (Asicon'07), Oct 2007, Guilin, China. pp.930-933, ⟨10.1109/ICASIC.2007.4415784⟩
Conference papers
hal-00222941v1
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Message-Oriented Devices on FPGAsInternational Symposium on Rapid System Prototyping (RSP 2018), Oct 2018, Torino, Italy. pp.8-14
Conference papers
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Fast Memory Consistency Analysis using Non-Intrusive Simulation TracesThe 2011 System, Software, SoC and Silicon Debug Conference (S4D), Sep 2011, Munich, Germany. pp.17-22
Conference papers
hal-00671512v1
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Dynamic Binary Translation of VLIW Codes on Scalar ArchitecturesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2017, 36 (5), pp.789-800. ⟨10.1109/TCAD.2016.2604294⟩
Journal articles
hal-01570692v1
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A Toolbox to Map System Level Communications on HW/SW Architectures12th International Workshop on Rapid System Prototyping, Jun 2001, Monterey, CA, United States. pp.77-82, ⟨10.1109/IWRSP.2001.933842⟩
Conference papers
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Périphériques Orientés Message sur FPGAConférence d’informatique en Parallélisme, Architecture et Système (COMPAS 2018), Jul 2018, Toulouse, France. pp.1-9
Conference papers
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Synthesis of communication mechanisms for multi-tile systemsbased on heterogeneous Multi-processor System-on-Chips20th IEEE/IFIP International Symposium on Rapid System Prototyping(RSP'09), Jun 2009, Paris, France. pp.48-54, ⟨10.1109/RSP.2009.12⟩
Conference papers
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A System Framework for the Design of Embedded Software Targeting Heterogeneous Multi-Core SoCs20th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP'09), Jul 2009, Boston (Ma), United States. pp.153-160, ⟨10.1109/ASAP.2009.9⟩
Conference papers
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Composant de traitement d'un signal numérique, dispositif de modulation et/ou de démodulation multiporteuse, procédé de modulation et/ou de démodulation et programme d'ordinateur correspondantsFrance, N° de brevet: WO/2008/145915 / PCT/FR2008/050703. http://www.wipo.int/pctdb/en/wo.jsp?WO=2008145915. 2008
Patents
hal-00570292v1
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Automatic instrumentation of embedded software for high level hardware/software co-simulationAsia and South Pacific Design Automation Conference (ASP-DAC'09), Jan 2009, Yokohama, France. pp.546-551, ⟨10.1109/ASPDAC.2009.4796537⟩
Conference papers
hal-00418912v1
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On MPSoC Software Execution at the Transaction LevelIEEE Design & Test, 2011, 28 (3), pp.32-43. ⟨10.1109/MDT.2010.118⟩
Journal articles
hal-00680474v1
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Modélisation des interfaces matériel/logiciel1ère école d'hiver francophone sur les systèmes hétérogènes, Jan 2007, Villard-de-Lans, France
Conference papers
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Formal Extraction of Memorizing Elements for Sequential VHDL SynthesisIEEE/EUROMICRO'98 International Conference on Digital Sytems, Aug 1998, Vasteras, Sweden. pp.317-320, ⟨10.1109/EURMIC.1998.711818⟩
Conference papers
hal-01618351v1
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Loop aware IR-level annotation framework for performance estimation in native simulation22nd Asia and South Pacific Design Automation Conference (ASPDAC 2017), Jan 2017, Chiba, Japan. pp.220-225
Conference papers
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