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sorted by
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Quantization Modes for Neural Network Inference: ASIC Implementation Trade-offsInternational Joint Conference on Neural Networks (IJCNN 2023), Jun 2023, Gold Coast, Australia. ⟨10.1109/IJCNN54540.2023.10191784⟩
Conference papers
hal-04188362v1
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128-bit addresses for the masses (of memory and devices)HotInfra 2023 - Workshop on Hot Topics in System Infrastructure, Jun 2023, Orlando, United States. 2023
Poster communications
hal-04161640v1
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We had 64-bit, yes. What about second 64-bit?RISC-V Summit Europe 2023, Jun 2023, Barcelona, Spain. 2023
Poster communications
hal-04161612v1
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A gem5-based CVA6 Framework for Microarchitectural PathfindingRISC-V Summit Europe 2023, Jun 2023, Barcelona, Spain
Poster communications
hal-04161617v1
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Fast Instruction Cache Simulation is Trickier than You ThinkDroneSE and RAPIDO: System Engineering for constrained embedded systems (RAPIDO 2023), Jan 2023, Toulouse, France. pp.48-53, ⟨10.1145/3579170.3579261⟩
Conference papers
hal-04131264v1
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Élimination des appels externes des accès mémoire dans la traduction binaire dynamiqueISTE. Systèmes multiprocesseurs sur puce 1 - Architectures, ISTE - International Scientific and Technical Encyclopedia, pp.171-203, 2023, ⟨10.51926/ISTE.9021.ch7⟩
Book sections
hal-04131343v1
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Cohérence des communications lors de la migration de tâches matériellesISTE. Systèmes multiprocesseurs sur puce 1 - Architectures, ISTE - International Scientific and Technical Encyclopedia, pp.309-343, 2023, ⟨10.51926/ISTE.9021.ch11⟩
Book sections
hal-04131346v1
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Méthodes matérielles de distribution des accès en banc mémoireISTE. Systèmes multiprocesseurs sur puce 1 - Architectures, ISTE - International Scientific and Technical Encyclopedia, pp.205-240, 2023, ⟨10.51926/ISTE.9021.ch8⟩
Book sections
hal-04131345v1
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Systèmes multiprocesseurs sur puce 2 - ApplicationsISTE - International Scientific and Technical Encyclopedia, 2023, 978-1-78948-022-1
Books
hal-04131348v1
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Toward Practical 128-bit General Purpose MicroarchitecturesIEEE Computer Architecture Letters, 2023, 22 (2), pp.81-84. ⟨10.1109/LCA.2023.3287762⟩
Journal articles
hal-04157369v1
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Systèmes multiprocesseurs sur puce 1 - ArchitecturesISTE - International Scientific and Technical Encyclopedia, 2023, 978-1-78948-021-4
Books
hal-04131338v1
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Abstracting Hardware Architectures for Agile Design of High-performance Applications on FPGAMicro and nanotechnologies/Microelectronics. Université Grenoble Alpes [2020-..], 2022. English. ⟨NNT : 2022GRALT096⟩
Theses
tel-04019979v1
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Exploring Instruction Fusion Opportunities in General Purpose Processors55th IEEE/ACM International Symposium on Microarchitecture (MICRO 2022), Oct 2022, Chicago, United States. ⟨10.1109/MICRO56248.2022.00026⟩
Conference papers
hal-03856365v1
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Low-precision logarithmic arithmetic for neural network accelerators33rd IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2022), IEEE, Jul 2022, Gothenburg, Sweden. ⟨10.1109/ASAP54787.2022.00021⟩
Conference papers
hal-03684585v1
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High Performance General Purpose Architecture and Microarchitecture16ème Colloque du GDR SoC2 (GDR SoC 2 2022), Jun 2022, Strasbourg, France
Conference papers
hal-04161879v1
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Free Atomics: Hardware Atomic Operations Without FencesInternational Symposium on Computer Architecture (ISCA 2022), Jun 2022, New-York, United States. pp.1-13, ⟨10.1145/3470496.3527385⟩
Conference papers
hal-03719531v1
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Leveraging Hardware Construction Languages for Flexible Design Space Exploration on FPGAMicro and nanotechnologies/Microelectronics. Université Grenoble Alpes [2020-..], 2022. English. ⟨NNT : 2022GRALT025⟩
Theses
tel-03709710v1
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Industrial AI Technologies for Next-Generation Autonomous Operations with Sustainable PerformanceIndustrial AI Technologies for Next-Generation Autonomous Operations with Sustainable Performance, River Publishers, pp.1-71, 2022, 9788770226103. ⟨10.13052/rp-9788770226103⟩
Book sections
hal-03740547v1
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Lossless Differential Table Compression for Hardware Function EvaluationIEEE Transactions on Circuits and Systems II: Express Briefs, 2021, ⟨10.1109/TCSII.2021.3131405⟩
Journal articles
hal-03040364v2
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Hardware-friendly AI algorithms: Ternary Neural NetworksHiPEAC Computing Systems Week (HiPEAC 2021), Oct 2021, Lyon (virtuel), France
Conference papers
hal-03417446v1
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Leveraging Targeted Value Prediction to Unlock New Hardware Strength Reduction PotentialIEEE/ACM International Symposium on Microarchitecture (MICRO 2021), Oct 2021, Athens, Greece
Conference papers
hal-03325303v1
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Exploration of Direct Synchronization Approaches for a High-Level and Unified Simulation of Discrete-Event/Continuous-Time SystemsModeling and Simulation. Université Grenoble Alpes [2020-..], 2021. English. ⟨NNT : 2021GRALM047⟩
Theses
tel-03625797v1
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Integrating Quick Resource Estimators in Hardware Construction Framework for Design Space Exploration2021 IEEE International Workshop on Rapid System Prototyping (RSP), Oct 2021, Paris, France. pp.64-70, ⟨10.1109/RSP53691.2021.9806276⟩
Conference papers
hal-03724027v1
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To Pin or Not to Pin: Asserting the Scalability of QEMU Parallel Implementation24th Euromicro Conference on Digital System Design (Euromicro DSD/SEAA 2021), Sep 2021, Palermo, Italy. pp.238-245, ⟨10.1109/DSD53832.2021.00045⟩
Conference papers
hal-03417343v1
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Compilation and optimizations for variable precision floating-Point arithmetic : from language and libraries to code generationComputer Arithmetic. Université Grenoble Alpes [2020-..], 2021. English. ⟨NNT : 2021GRALM020⟩
Theses
tel-03414534v1
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Efficient deep learning approach for fault detection in the semiconductor industryADTC 2021 - European Nanoelectronics Applications Design & Technology Conference, Jun 2021, Grenoble, France
Conference papers
hal-03421323v1
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Component Based Framework for Designing and Validating Asynchronous Algorithms for Electrical Measurement and Protection4th IEEE International Conference on Industrial Cyber-Physical Systems (ICPS 2021), May 2021, Victoria, BC, Canada. ⟨10.1109/ICPS49255.2021.9468117⟩
Conference papers
hal-03432269v1
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Seamless Compiler Integration of Variable Precision Floating-Point ArithmeticInternational Symposium on Code Generation and Optimization (CGO 2021), Feb 2021, Atlanta, United States
Conference papers
hal-03169752v1
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Integrating devices in FPGA using an end-to-end hardware/software co-designedmessage-based approachEmbedded Systems. Université Grenoble Alpes [2020-..], 2021. English. ⟨NNT : 2021GRALM004⟩
Theses
tel-03259401v1
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RISC-V Online Tutor and LabInternational Conference on Remote Engineering and Virtual Instrumentation (REV 2021), Feb 2021, Hong Kong, Hong Kong SAR China
Conference papers
hal-03194370v1
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Arbitrary and Variable Precision Floating-Point Arithmetic Support in Dynamic Binary Translation26th Asia and South Pacific Design Automation Conference (ASP-DAC 2021), Jan 2021, Tokyo (Virtual event), Japan
Conference papers
hal-03117382v1
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Simulation of Ideally Switched Circuits in SystemCAsia and South Pacific Design Automation Conference (ASP-DAC 2021), Jan 2021, Tokyo, Japan
Conference papers
hal-03020808v1
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AI in Semiconductor IndustryArtificial Intelligence for Digitising Industry, River Publishers, pp.105-112, 2021, 9788770226646. ⟨10.13052/rp-9788770226639⟩
Book sections
hal-03421047v1
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Refinement rules for the automatic TLM-to-RTL conversion of temporal assertionsIntegration, the VLSI Journal, 2021, 76, pp.190-204. ⟨10.1016/j.vlsi.2020.06.003⟩
Journal articles
hal-03110673v1
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A Non-intrusive Tool Chain to Optimize MPSoC End-to-end SystemsACM Transactions on Architecture and Code Optimization, 2021, 18 (2), pp.1 - 22. ⟨10.1145/3445030⟩
Journal articles
hal-03193879v1
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Synchronization of Continuous Time and Discrete Events Simulation in SystemCIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2021, 40 (7), pp.1450 - 1463. ⟨10.1109/TCAD.2020.3019204⟩
Journal articles
hal-02926338v1
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A Case for Speculative Strength ReductionIEEE Computer Architecture Letters, 2021, 20 (1), pp.22-25. ⟨10.1109/LCA.2020.3048694⟩
Journal articles
hal-03138881v1
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Multi-Processor System-on-Chip 2: Applicationswiley, chichester, uk, 2, pp.272, 2021, 978-1-119-81840-3
Books
hal-03193978v1
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Removing Load/Store Helpers in Dynamic Binary TranslationMulti‐Processor System‐on‐Chip, iste - international scientific and technical encyclopedia, pp.133-160, 2021, 9781789450217. ⟨10.1002/9781119818298.ch7⟩
Book sections
hal-03245419v1
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Study and Comparison of Hardware Methods for Distributing Memory Bank Accesses in Many-core ArchitecturesMulti-Processor System-on-Chip 1: Architectures, wiley, chichester, uk, pp.161-194, 2021, 978-1-789-45021-7
Book sections
hal-03195677v1
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Multi-Processor System-on-Chip 1: Architectureswiley, chichester, uk, 1, pp.320, 2021, 978-1-789-45021-7
Books
hal-03194277v1
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Hardware Context Switch-based Cryptographic Accelerator for Handling Multiple StreamsACM Transactions on Reconfigurable Technology and Systems (TRETS), 2021
Journal articles
hal-03352889v1
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Efficient Deep Learning Approach for Fault Detection in the Semiconductor IndustryOvidiu VERMESAN. Artificial Intelligence for Digitising Industry – Applications, River Publishers, pp.131-143, 2021, 978-87-7022-664-6
Book sections
hal-03782453v1
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Towards Agile Hardware Designs with Chisel: a Network Use-caseIEEE Design & Test, 2021, ⟨10.1109/MDAT.2021.3063339⟩
Journal articles
hal-03157426v1
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Maintaining Communication Consistency during Task Migrations in Heterogeneous Reconfigurable DevicesMulti-Processor System-on-Chip 1: Architectures, wiley, chichester, uk, pp.255-285, 2021, 978-1-789-45021-7
Book sections
hal-03194391v1
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VP Float: First Class Treatment for Variable Precision Floating Point ArithmeticInternational Conference on Parallel Architectures and Compilation Techniques (PACT 2020), Oct 2020, Atlanta, United States. pp.355-356, ⟨10.1145/3410463.3414660⟩
Conference papers
hal-03108836v3
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(System)Verilog to Chisel Translation for Faster Hardware Design2020 31th International Symposium on Rapid System Prototyping (RSP), Sep 2020, VIrtual Conference, France
Conference papers
hal-02949112v1
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Virtual Prototyping of Open Source Heterogeneous Systems with an Open Source Framework Featuring SystemC MDVP Extensions2020 Forum for Specification and Design Languages (FDL), Sep 2020, Kiel, Germany. pp.1-8, ⟨10.1109/FDL50818.2020.9232947⟩
Conference papers
hal-03065588v1
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Low Power Tiny Binary Neural Network with improved accuracy in Human Recognition SystemsEuromicro Conference on Digital System Design (DSD 2020), Aug 2020, Kranj (virtual), Slovenia. pp.309-315, ⟨10.1109/DSD51259.2020.00057⟩
Conference papers
hal-03106955v1
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Implementation and Evaluation of a Hardware Decentralized Synchronization Lock for MPSoCsInternational Parallel and Distributed Processing Symposium (IPDPS 2020), May 2020, New Orleans, United States. pp.1112-1121
Conference papers
hal-03194329v1
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Lock manager for multi-core architecturesUnited States, Patent n° : US 20200097336 A1. 2020
Patents
hal-02108564v1
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Accurate and Efficient Continuous Time and Discrete Events Simulation in SystemCDesign, Automation and Test in Europe (DATE 2020), Mar 2020, Grenoble, France
Conference papers
hal-02359109v1
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State of the art in hardware-accelerated neural networksApplied Machine Learning Days (AMLD 2020), Jan 2020, Lausanne, Switzerland
Conference papers
hal-03185600v1
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