Poster De Conférence Année : 2026

Automatic Extraction of Timing Models for WCET Estimation from a High-Level Synthesis Flow

Résumé

Real-time, domain-specific processors require faithful timing models for WCET analysis. However, existing models are typically hand-crafted from sparse documentation, making them error-prone and difficult to maintain. This work aims to automatically extract WCET timing models from single-issue in-order processor pipelines generated by High-Level Synthesis (HLS). By deriving timing models directly from the SpecHLS intermediate representation, the models are faithful by construction. Experimental results show that our timing-model extraction process generalizes across diverse RISC-V core variants and yields WCET estimates within 0.48% on average of those from a handcrafted model, on the Mälardalen WCET benchmarks.

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Complète hal-05365718 Objet présenté à une conférence Thomas Feuilletin, Dylan Leothaud, Simon Rokicki, Steven Derrien, Isabelle Puaut. Automatic Extraction of Timing Models for WCET Estimation From a High-Level Synthesis Flow. DATE 2026 - Design, Automation and Test in Europe Conference, Apr 2026, Verona, Italy. ⟨hal-05365718⟩

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hal-05601264 , version 1 (24-04-2026)

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  • HAL Id : hal-05601264 , version 1

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Thomas Feuilletin, Dylan Leothaud, Simon Rokicki, Steven Derrien, Isabelle Puaut. Automatic Extraction of Timing Models for WCET Estimation from a High-Level Synthesis Flow. DATE 2026 - Design, Automation and Test in Europe Conference, Apr 2026, Vérone, Italy. 2026. ⟨hal-05601264⟩
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