A 100 V Input Common-Mode Range Compact Three-Step Incremental ADC Architecture Evaluation Achieving 101.48 dB SNDR and 6.46 µV RMS Input-Referred Noise
Résumé
This work presents a novel system-level architecture for the Three-Step Zoom-Incremental-Extended-Counting Analog-to-Digital Converter (ADC), designed to minimize area and power consumption while maintaining high resolution. It requires only a single sampling stage, integrator, multi-bit Digital-to-Analog Converter and 1.5-bit comparator across all three conversion phases, eliminating the need for additional interfacing circuits. The proposed ADC is tailored for High-Voltage (HV) applications, operating within a constrained design space compared to standard literature. It achieves unprecedented HV Input Common-Mode capabilities of 100 V and the highest peak SNDR among HV ADCs, with the smallest sampling capacitance (1.25 pF), area (0.45 mm2 ) and power consumption (240 µW). Unlike higher-order free-running ∆Σ modulators in HV literature, this design employs a simpler first-order incremental conversion, enabling input multiplexing and further simplifying the design. To our knowledge, it is also the first Zoom-Incremental-Extended-Counting ADC architecture with HV capabilities. Operating at a sampling frequency of 1 MHz, the proposed ADC achieves a simulated Signal-to-Noise-and-Distortion-Ratio of 101.48 dB and input-referred noise of 6.46 µV RMS , for a conversion time of 4.14 ms. Expected area is 0.45 mm2 in a 0.11-µm BCD technology, making it highly suitable for space-constrained, power-efficient HV monitoring systems.
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