Communication Dans Un Congrès Année : 2025

Efficient Negative Weight Realization for Analog Resistive Neural Networks

Résumé

Most analog nonlinear resistive neural networks for machine learning training use doubling input and output neuron nodes to implement negative weights. However, this approach increases network size, modifies the gradient computation, and complicates circuit design. We propose an alternative circuit topology that retains a one-to-one correspondence between neurons in the original model and their analog counterparts. Our design employs a emph{single} input source for all first-layer weights, a emph{single} resistor per weight, and a bidirectional amplifier for the rest of the layers' weight to handle negative connections without duplicating neurons. We validate our design on a binary XOR classification task over SI{100}{} training epochs and SI{100}{} randomized initializations. Our textbf{single-resistor} approach achieved an average final error of SI{-6.6}{dB} and required approximately SI{568}{} minutes of total CPU time. In comparison, the textbf{doubled-node} design reached SI{-4.6}{dB} error and consumed around SI{1104}{} minutes of CPU time. This equates to nearly 49% less computation for the single-resistor circuit while preserving the standard gradient update procedure—demonstrating that negative weights can be realized more efficiently without doubling input/output neurons.

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Dates et versions

hal-05230077 , version 1 (29-08-2025)

Identifiants

  • HAL Id : hal-05230077 , version 1

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Zulal Kiraz, Dang-Kièn Germain Pham, Patricia Desgreys. Efficient Negative Weight Realization for Analog Resistive Neural Networks. 68th IEEE International Midwest Symposium on Circuits and Systems, IEEE, Aug 2025, Lansing, MI, United States. ⟨hal-05230077⟩
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