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                <term xml:lang="en">Secure code generation</term>
                <term xml:lang="en">Physical attacks Secure code generation Hardware/Software co-design RISC-V</term>
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              <p>This article puts forward the idea of a co-design, between the hardware and the software of a computer system, combining hardware security features with code generation. We propose as a first contribution a countermeasure to a side channel attack that reduces the amount of critical information passing through vulnerable components, i.e. the bus and the cache. This solution consists of minimizing the spill of a critical data by integrating a pass, occurring between the instruction selection and the register allocation of a compiler. The method will be evaluated on RISC-V 32b processors.</p>
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