Preliminary 2D elastoplastic modeling of gate cracking in SiC MOSFETs under short-circuit conditions across a wide temperature-range using rankine's damage energetic approach. (Selected – Extended Full Paper from ESREF'24)
Résumé
For the first time in SiC MOSFETs, structural and physical modeling of the Intermediate-Layer-Dielectric (ILD) cracking in a planar gate under short-pulse short-circuit conditions is proposed. This approach employs an energy-based Rankine damage model, relying on the SiO2 mechanical properties. The Rankine model has been effectively integrated into a comprehensive 2D electrothermal-metallurgical and elastoplastic-mechanical model across a wide range of temperatures. Initial results enable the extraction of crack penetration depth from a single pulse, paving the way for estimating the average number of critical cycles leading to a potentially complete destructive ILD fracture.
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