Leveraging gem5 for Hardware Trojan Research: Simulation for Machine-Learning-Based Detection
Résumé
Hardware Trojans (HTs) consist of malicious modifications intentionally embedded in hardware designs, capable of bypassing security measures, leaking sensitive information, or disrupting system operations. This work proposes a methodology for introducing and simulating HTs on microprocessor-based systems within the gem5 simulator, focusing on RISC-V architectures. By leveraging the gem5 System Emulation (SE) mode, we generate comprehensive datasets encompassing both benign and attack scenarios, automating the collection of 866 features from Hardware Performance Counters (HPC) dumped by gem5 after every program run. The dataset consists of 10,000 samples, evenly split into 5,000 benign and 5,000 attacked instances on different runs across 8 benchmarks. Contrary to previous work using processors with a very limited number of HPCs, we demonstrate how simulation provides access to a much larger number of HPCs and can, hence, enable new research on effective detection mechanisms. In particular, we show preliminary results for one HT and improve previous work on detection mechanisms using Machine Learning (ML). Using a Random Forest (RF) classifier and taking inspiration from the PIC16F84-T100 HT from the Trust-Hub platform as a case study, we achieve 100% attack detection. Our approach facilitates the security evaluation of microprocessors under HT attacks and provides a framework for experimenting with and analyzing ML-based detection strategies.
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