Communication Dans Un Congrès Année : 2025

A hardware design methodology to prevent microarchitectural transition leakages

Résumé

Side-channel attacks allow information extraction from a system by analyzing indirect observations. For instance, power consumption is known to be correlated with sensitive data manipulated by digital components. Recent efforts have been put on securing the system at the software level with a formally proven method called masking. They rely on an abstract model of the target where automatic countermeasures can be efficiently applied. Recent work focused on microarchitecture, i.e. implementation details of the hardware, to deal with residual vulnerabilities which require strong knowledge of the system's hardware and have limited portability. In this paper, we present a generic methodology to harden the processor's microarchitecture to allow straightforward software defense strategy implementation (like masking) with minimal knowledge of the hardware. Based on a fine-grained vulnerability diagnosis at the microarchitecture level and a generic design hardening strategy, our proposition can be applied to produce several processors with security, performance and area tradeoffs. In addition, we provide two secured designs based on a customizable RISC-V processor and its memories, validated with real measurements on an FPGA.

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Dates et versions

hal-05042726 , version 1 (22-04-2025)

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  • HAL Id : hal-05042726 , version 1

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Mathieu Escouteloup, Vincent Migliore. A hardware design methodology to prevent microarchitectural transition leakages. CASCADE 2025, Apr 2025, Saint-Etienne (FR), France. ⟨hal-05042726⟩
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