Enforcing RISC-V TEE Security Against Cache Timing Attacks
Résumé
Confidential computing includes various methods to enhance data security, notably by processing sensitive information within TEE. However, TEE remain vulnerable to SCA, such as cache timing attacks, which exploit timing variations to extract confidential data. Existing TEE designs do not provide sufficient protection against these threats, highlighting the need for stronger security measures. This study focuses on integrating countermeasures specifically targeting timing and cache vulnerabilities within a TEE. The implementation will leverage the RISC-V architecture to explore its potential in mitigating SCA within TEE.