Communication Dans Un Congrès Année : 2024

Bit-Accurate RTL Simulation of an NQR Spectrometer's SoC-FPGA

Résumé

This paper presents a comprehensive verification environment and methodology for fully verifying a System on Chip-Field-Programmable Gate Array (SoC-FPGA) used in building an NQR spectrometer through RTL simulation. The verification environment includes an RTL testbench, a database of tests, design modules simulation models, and simulation automation scripts. Initially, the system is simulated in an RTL testbench written in System Verilog, with the SoC-FPGA as the Device Under Test (DUT). To simulate real NMR/NQR experiments, various tests are created, each corresponding to a specific experiment, comprising stimuli, current test configuration files and reference files. For each test, the simulation output files of the DUT are compared bit-wise to the reference files. Simulation and check scripts provide a snapshot of the design's non-regression status. This methodology and platform enable in-depth verification of the SoC-FPGA's functionality, significantly reducing the experimental validation time of the NQR spectrometer on real samples. Future enhancements could include verifying the signal denoising algorithms implemented on the SoC-FPGA.

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Dates et versions

hal-04926431 , version 1 (03-02-2025)

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Noreddine Kachkachi, Hassan Rabah. Bit-Accurate RTL Simulation of an NQR Spectrometer's SoC-FPGA. 31st IEEE International Conference on Electronics, Circuits and Systems (ICECS), Nov 2024, Nancy, France. pp.1-4, ⟨10.1109/ICECS61496.2024.10849348⟩. ⟨hal-04926431⟩
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