Communication Dans Un Congrès Année : 2019

A 3.2–3.6GHz SOI-LDMOS Dual-Input Doherty Power Amplifier

Résumé

This work presents a SOI-LDMOS Dual-Input Doherty Power Amplifier (DPA). The proposed DPA is implemented in a 130nm SOI-CMOS technology and packaged using flip-chip on a laminate substrate. Low DPA combiner loss is achieved using high-Q inductors embedded onto the laminate. The proposed Doherty PA exhibits a measured peak output power of 30 dBm at 3.2GHz, under 3.4V voltage supply. The peak Power-Added Efficiency (PAE) is 40%, and PAE at 27dBm output power is 37%. With a 10MHz LTE signal, the linearized DPA achieves a measured ACLR of -42 dBc at 27dBm output power.

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Dates et versions

hal-04911387 , version 1 (24-01-2025)

Identifiants

Citer

Saad Boutayeb, Ayssar Serhan, Pascal Reynier, Damien Parat, Alexis Divay, et al.. A 3.2–3.6GHz SOI-LDMOS Dual-Input Doherty Power Amplifier. IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S 2019), Oct 2019, San Jose (CA), United States. ⟨10.1109/S3S46989.2019.9320747⟩. ⟨hal-04911387⟩
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