LUT-based design of a cryogenic cascode LNA with simultaneous noise and power matching - Archive ouverte HAL
Communication Dans Un Congrès Année : 2024

LUT-based design of a cryogenic cascode LNA with simultaneous noise and power matching

Résumé

In recent years, cryogenic silicon electronics have gained increased interest for applications in fields such as quantum computers and space exploration. Unfortunately, commercial technologies lack cryogenic compact models for circuit design. In this paper, we target the sizing of the critical input stage of a power efficient low-noise amplifier working at 7 GHz and 4 K with simultaneous noise and power matching for meeting the stringent specifications of a gate-dispersive readout circuit for spin quantum bits. In the absence of a compact model for the transistors in 28 nm FD-SOI technology, we propose a design methodology using a look-up table that has been buit with 4 K DC measurements of technology transistors and their associated capacitors to demonstrate the feasibility of the circuit.

Mots clés

LNA
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Dates et versions

hal-04789177 , version 1 (18-11-2024)

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Giovani Crasby Britton Orozco, Salvador Mir, Estelle Lauga-Larroze, Benjamin Dormieu, José Lugo-Alvarez, et al.. LUT-based design of a cryogenic cascode LNA with simultaneous noise and power matching. NEWCAS 2024 - 22nd IEEE International NEWCAS Conference, Jun 2024, Sherbrooke, Canada. pp.65-69, ⟨10.1109/NEWCAS58973.2024.10666334⟩. ⟨hal-04789177⟩
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