Article Dans Une Revue IEEE Transactions on Circuits and Systems I: Regular Papers Année : 2024

An Incremental Time-Domain Mixed-Signal Matrix-Vector-Multiplication Technique for Low-Power Edge-AI

Résumé

This paper proposes a time-domain mixed-signal computing architecture for Matrix-Vector Multiplication suited for embedded in-memory computing applications. The system leverages the low data rate of sensors’ data in embedded AI applications to target an energy-efficient implementation of the matrix-vector multiplication array. The mixed-signal computing scheme relies on incremental time-domain multiply-and-accumulate operations using switched current sources. The concept is demonstrated on a 28 nm FDSOI prototype chip of a 100 × 4 compute array that shows a 15.8 TOPS/W energy efficiency for 5-bit MAC operations. Extrapolating the array to 100 × 100 computing units leads to a 99.2 TOPS/W energy efficiency.

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hal-04765787 , version 1 (04-11-2024)

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Kévin Hérissé, Benoit Larras, Bruno Stefanelli, Andreas Kaiser, Antoine Frappé. An Incremental Time-Domain Mixed-Signal Matrix-Vector-Multiplication Technique for Low-Power Edge-AI. IEEE Transactions on Circuits and Systems I: Regular Papers, In press, pp.1-12. ⟨10.1109/TCSI.2024.3480154⟩. ⟨hal-04765787⟩
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