Article Dans Une Revue Solid-State Electronics Année : 2024

Methodology for parameters extraction with undoped junctionless EZ-FETs

Résumé

The junctionless EZ-FET is a simple FDSOI-like device that requires only two lithography levels and standard processing steps. With its simplified architecture and fabrication flow, and using undoped source and drain terminals, the device allows for a fast electrical evaluation of semiconductor films on insulators (SOI) and gate stacks. This paper describes an electrical model that reproduces the peculiar transfer characteristics of a junctionless EZ-FET. The model is then simplified to develop a pragmatic parameter extraction methodology. This methodology is experimentally validated and provides the electrical properties of SOI films (mobility, threshold voltage) for both electrons and holes.

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Dates et versions

hal-04742900 , version 1 (18-10-2024)

Identifiants

Citer

N. Zerhouni Abdou, S. Reboh, L. Brunet, M. Alepidis, P. Acosta Alba, et al.. Methodology for parameters extraction with undoped junctionless EZ-FETs. Solid-State Electronics, 2024, 217, pp.108897. ⟨10.1016/j.sse.2024.108897⟩. ⟨hal-04742900⟩
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