Exploring RAPL as a Power Capping Leverage for Power-Constrained Infrastructures - Archive ouverte HAL
Communication Dans Un Congrès Année : 2024

Exploring RAPL as a Power Capping Leverage for Power-Constrained Infrastructures

Résumé

Data centers are very energy-intensive facilities whose power provision is challenging and constrained by power bounds. In modern data centers, servers account for a significant portion of the total power consumption. In this context, the ability to limit the instant power consumption of an individual computing node is an important requirement. There are several energy and power capping techniques that can be used to limit compute node power consumption, such as Intel RAPL. Although it is nowadays mainly utilized for energy measurement, Intel RAPL (Running Average Power Limit) was originally designed for power limitation purposes. Some works use Intel RAPL for power limitation in a limited context without full knowledge of the inner workings of this technology and what is done behind the scenes to enforce the power constraint. Furthermore, Intel has not revealed any details about its internal implementation. It is unclear exactly how Intel RAPL technology operates and what effects it has on application performance and power consumption. In this work, we conduct a thorough analysis of Intel RAPL technology as a power capping leverage on a variety of heterogeneous nodes for a selection of CPU and memory intensive workloads. For this purpose, we first validate Intel RAPL power capping mechanism using a high-precision external power meter and investigate properties such as accuracy, power limit granularity, and settling time. Then, we attempt to determine which mechanisms are employed by RAPL to adjust power consumption.
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Dates et versions

hal-04742418 , version 1 (17-10-2024)

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Identifiants

  • HAL Id : hal-04742418 , version 1

Citer

Vladimir Ostapenco, Laurent Lefèvre, Anne-Cécile Orgerie, Benjamin Fichel. Exploring RAPL as a Power Capping Leverage for Power-Constrained Infrastructures. ICA3PP 2024 - 24th International Conference on Algorithms and Architectures for Parallel Processing, Oct 2024, Macau SAR, China. pp.1-10. ⟨hal-04742418⟩
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