Hardware Implementation and FPGA Prototyping of an Expectation Propagation-based Receiver
Résumé
This paper presents a hardware implementation and FPGA prototyping of a flexible pipelined Expectation Propagation (EP)-based receiver that can handle QPSK, 8-PSK and 16-QAM constellations. The receiver implements a Frequency Domain (FD) Self-Iterated Linear Equalizer (SILE) based on EP to approximate the true posterior distribution of the transmitted symbols by a simpler distribution. Analytical approximations for the EP feedback generation process and the three constellations are applied to reduce the hardware complexity of the soft mapper/demapper architectures. The implementation results show a significant reduction in clock cycles due to the pipeline and an efficient usage of FPGA resources, underscoring the effectiveness of the proposed architecture.
Mots clés
Expectation Propagation
Frequency Domain Self-Iterated Linear Equalizer
Hardware Implementation
Architecture Design
FPGA prototyping
Pipelined Architecture
Expectation Propagation Frequency Domain Self-Iterated Linear Equalizer Hardware Implementation Architecture Design FPGA prototyping Pipelined Architecture
Expectation Propagation
Domaines
Architectures Matérielles [cs.AR]
Fichier principal
main.pdf (2.97 Mo)
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fig/FD_sile_simp.png (624.23 Ko)
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fig/all_pipe_sch.png (2.92 Mo)
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fig/b3_16qam_sch.png (1002.14 Ko)
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fig/b3_8psk_sch.png (1.23 Mo)
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fig/b3_qpsk_sch.png (781.43 Ko)
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fig/b4_16qam_sch.png (867.21 Ko)
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fig/b4_8psk_sch.png (1014.16 Ko)
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fig/b4_qpsk_sch.png (749.45 Ko)
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fig/b5_sch.png (909.24 Ko)
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fig/order_sch.png (1.22 Mo)
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fig/simplified_hil.png (501.78 Ko)
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