Communication Dans Un Congrès Année : 2024

Implementation of High-Speed Multi-Trit Adders for Balanced and Unbalanced Ternary Logic

Résumé

Ternary logic with larger data density has great potential in high-performance data processing. Even though ternary half/full adders have been intensively investigated in recent years, the high-speed multi-trit ternary adders, which are urgently needed for high-efficient ternary computing, remain unexplored. In this study, we present ternary carry lookahead adders (CLAs) to eliminate the tedious delay caused by the cascade-connected carry signals. Different implementation methods are used for unbalanced and balanced ternary logic. A delay analysis model of ternary CLAs is established. Compared with reported ternary carry ripple adders (CRAs), our 5-trit unbalanced and balanced ternary CLAs can achieve a 61.45% and 75.18% reduction in delay, respectively.

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Dates et versions

hal-04712618 , version 1 (27-09-2024)

Identifiants

Citer

Guangchao Zhao, Zhiwei Zeng, Huamin Jie, Xingli Wang, Philippe Coquet, et al.. Implementation of High-Speed Multi-Trit Adders for Balanced and Unbalanced Ternary Logic. 2024 13th International Conference on Communications, Circuits and Systems (ICCCAS), May 2024, Xiamen, China. pp.169-174, ⟨10.1109/ICCCAS62034.2024.10652734⟩. ⟨hal-04712618⟩
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