Communication Dans Un Congrès Année : 2024

Machine Learning-Based Classification of Hardware Trojans in FPGAs Implementing RISC-V Cores

Résumé

Hardware Trojans (HTs) pose a severe threat to integrated circuits, potentially compromising electronic devices, exposing sensitive data, or inducing malfunction. Detecting such malicious modifications is particularly challenging in complex systems and commercial CPUs, where they can occur at various design stages, from initial HDL coding to the final hardware implementation. This paper introduces a machine learningbased strategy for the detection and classification of HTs within RISC-V soft cores implemented in Field-Programmable Gate Arrays (FPGAs). Our approach comprises a systematic methodology for comprehensive data collection and estimation from FPGA bitstreams, enabling us to extract insights ranging from hardware performance counters to intricate metrics like design clock frequency and power consumption. Our ML models achieve perfect accuracy scores when analyzing features related to both synthesis, implementation results, and performance counters. We also address the challenge of identifying HTs solely through performance counters, highlighting the limitations of this approach. Additionally, our work emphasizes the significance of Implementation Features (IFs), particularly circuit timing, in achieving high accuracy in HT detection.

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Dates et versions

hal-04685628 , version 1 (03-09-2024)

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Stefano Ribes, Fabio Malatesta, Grazia Garzo, Alessandro Palumbo. Machine Learning-Based Classification of Hardware Trojans in FPGAs Implementing RISC-V Cores. ICISSP 2024 - 10th International Conference on Information Systems Security and Privacy, Feb 2024, Rome, Italy. pp.1-8, ⟨10.5220/0012324200003648⟩. ⟨hal-04685628⟩
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