Due to the expansion of defects like single Shockley-type Stacking Faults inside the SiC epitaxial drift layer, during high current stress, classical SiC MOSFETs can be victims of the degradation of their electrical characteristics. The introduction of an epitaxial SiC buffer layer between the substrate and the n- drift epilayer, called recombination-enhancing buffer layer, was shown to avoid this degradation. In this paper, TCAD simulations of the electrical behavior of such a commercial SiC MOSFET device with varying buffer layer thickness are studied, indicating only small modifications of the electrical characteristics. These simulations are combined with the characterization of the local electrical properties using an AFM-sMIM technique, allowing to determine the real thickness of the different layers of the device. These measurements highlight an inhomogeneous conductivity in the SiC substrate, being probably compensated by the introduction of the SiC buffer layer.