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Article Dans Une Revue Design Automation for Embedded Systems Année : 2010

Modular static scheduling of synchronous data-flow networks

Marc Pouzet
Pascal Raymond

Résumé

This paper addresses the question of producing modular sequential imperative code from synchronous data-flow networks. Precisely, given a system with several input and output flows, how to decompose it into a minimal number of classes executed atomically and statically scheduled without restricting possible feedback loops between input and output?

Though this question has been identified by Raymond in the early years of LUSTRE, it has almost been left aside until the recent work of Lublinerman, Szegedy and Tripakis. The problem is proven to be intractable, in the sense that it belongs to the family of optimization problems where the corresponding decision problem -there exists a solution with size c -is NP-complete. Then, the authors derive an iterative algorithm looking for solutions for c = 1, 2, ... where each step is encoded as a SAT problem.

Despite the apparent intractability of the problem, our experience is that real programs do not exhibit such a complexity. Based on earlier work by Raymond, this paper presents a new symbolic encoding of the problem in terms of input/output relations. This encoding simplifies the problem, in the sense that it rejects solutions, while keeping all the optimal ones. It allows, in polynomial time, (1) to identify nodes for which several schedules are feasible and thus are possible sources of combinatorial explosion; (2) to obtain solutions which in some cases are already optimal; (3) otherwise, to get a non trivial lower bound for c to start an iterative combinatorial search.

The solution applies to a large class of block-diagram formalisms based on atomic computations and a delay operator, ranging from synchronous languages such as LUSTRE or SCADE to modeling tools such as SIMULINK.

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Dates et versions

hal-04679268 , version 1 (27-08-2024)

Identifiants

Citer

Marc Pouzet, Pascal Raymond. Modular static scheduling of synchronous data-flow networks. Design Automation for Embedded Systems, 2010, 14 (3), pp.165-192. ⟨10.1007/s10617-010-9053-3⟩. ⟨hal-04679268⟩
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