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Conference Papers Year : 2024

SET sensitivity of a VCRO-based PLL for HL-LHC ATLAS HGTD

Abstract

We report the characterization of the Single Effect Transient (SET) sensitivity of an analogue Phase Locked Loop (PLL) based on a Voltage Controlled Ring Oscillator (VCRO) under a proton beam. The clock generator is embedded in a front-end ASIC, namely ALTIROC designed in CMOS 130 nm, reading out Low-Gain Avalanche Diode (LGAD) matrices for the High-Luminosity Large Hadron Collider (HL-LHC). We detail the methodology developed to study such events that could degrade the targeted time resolution of 35 ps per hit. Observed SET-induced phase jumps allow the estimation of the total cross-section of the PLL. The results are extrapolated to the HL-LHC radiation conditions.

Dates and versions

hal-04537647 , version 1 (08-04-2024)

Identifiers

Cite

Christophe de la Taille, Pierrick Dinaucourt, Beng-Yun Ky, Maxime Morenas, Nathalie Seguin-Moreau, et al.. SET sensitivity of a VCRO-based PLL for HL-LHC ATLAS HGTD. Topical Workshop on Electronics for Particle Physics, Oct 2023, Geremeas, Italy. pp.C04014, ⟨10.1088/1748-0221/19/04/C04014⟩. ⟨hal-04537647⟩
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