Due to its high parallelism, belief propagation (BP) decoding is amenable to high-throughput applications and thus represents a promising solution for the ultra-high peak data rate required by future communication systems. To bridge the performance gap compared to the widely used successive cancellation list (SCL) decoding algorithm, BP list (BPL) decoding for polar codes extends candidate codeword exploration via multiple permuted factor graphs (PFGs) to improve the error-correcting performance of BP decoding. However, it is a significant challenge to design a unified and flexible BPL hardware architecture that supports various PFGs and code configurations. In this paper, we present the first VLSI implementation of a BPL decoder for polar codes that overcomes this implementation challenge with a hardware-friendly algorithm for on-the-fly flexible permutations. First, we introduce a sequential generation (SG) algorithm to obtain a near-optimal PFG set. Additionally, we demonstrate that any permutation can be decomposed into a combination of multiple fixed routings, and design a low-complexity permutation network to generate graphs in an on-the-fly fashion. Our BPL decoder has a low decoding latency by executing decoding and permutation generation in parallel and supports arbitrary list sizes without area overhead. Experimental results based on 28 nm FD-SOI technology show that for length- 1024 polar codes with a code rate of one-half, our BPL decoder with 32 PFGs exhibits similar error-correcting performance to SCL with a list size of 4 and achieves an average throughput of 25.63 Gbps and an area efficiency of 29.46 Gbps/mm$^{2}$ , which is 1.82 × and 4.33 × faster than the state-of-the-art BP flip and SCL decoders, respectively.