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Communication Dans Un Congrès Année : 2023

Efficient Co-Design Methodology combinig Fast and Accurate System-level Simulations with Transistor-level Characterization

Résumé

The Charge-Pump PLL (CP-PLL) stays one of the most popular circuit topologies used for frequency synthesis. Because of its mixed-signal nature, no established linear theory allows an exact description of its behavior, making its design challenging. In this paper an efficient design approach of the CP-PLL is presented achieving accuracy and time efficiency while considering nonlinear and non-ideal effects. A very efficient event-driven simulation model is combined with a CMOS-based design approach. The extracted macroscopic parameters are used at the behavioral level in order to allow a very fast but accurate closed-loop simulation, leading to a robust top-down and bottom-up co-design methodology.
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Dates et versions

hal-04524666 , version 1 (28-03-2024)

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Mathieu Guerin, Fayrouz Haddad, Md-Hossain Sazzad, Ivan Kaufmann, Christian Hedayat, et al.. Efficient Co-Design Methodology combinig Fast and Accurate System-level Simulations with Transistor-level Characterization. 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2023), Dec 2023, Istanbul, Turkey. pp.1-4, ⟨10.1109/ICECS58634.2023.10382733⟩. ⟨hal-04524666⟩
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