RISC-V Embedded AI for IDS Applications
Pierre Garreau
(1, 2, 3)
,
Pascal Cotret
(1, 4)
,
Julien Francq
(5)
,
Jean-Christophe Cexus
(6, 4)
,
Loïc Lagadec
(1, 4)
Pierre Garreau
- Fonction : Auteur
- PersonId : 1362129
Pascal Cotret
- Fonction : Auteur
- PersonId : 4600
- IdHAL : pcotret
- ORCID : 0000-0001-6325-0777
Jean-Christophe Cexus
- Fonction : Auteur
- PersonId : 3110
- IdHAL : jean-christophe-cexus
- ORCID : 0000-0003-2635-1768
- IdRef : 095145044
Loïc Lagadec
- Fonction : Auteur
- PersonId : 2758
- IdHAL : loic-lagadec
- ORCID : 0000-0003-3778-3144
- IdRef : 16903870X
Résumé
IDSs (Intrusion Detection Systems) include more and more AI (Artificial Intelligence) engines to detect several attack types. However, in order to be efficient in both learning and inference phases, such systems must include hardware coprocessors to improve AI-related computations. In this PhD thesis, we would like to explore the capabilities of RISC-V based processors in this context. RISC-V is an open-source ISA (Instruction Set Architecture) than can be easily extended. The main goal of this thesis is to propose RISC-V extensions for an IDS embedded into collaborative and heterogeneous unmanned vehicles (submarine, marine, or aerial): it must detect abnormal behaviors and must be efficient in terms of power consumption, area and runtime overheads. Furthermore, coprocessors developed in this thesis should not introduce security breaches into the system. Finally, a proof-of-concept should be developed to demonstrate the efficiency of algorithms and hardware implementations compared to software solutions.
Domaines
Cryptographie et sécurité [cs.CR] Intelligence artificielle [cs.AI] Architectures Matérielles [cs.AR]Format du dépôt | Fichier |
---|---|
Type de dépôt | Communication dans un congrès |
Résumé |
en
IDSs (Intrusion Detection Systems) include more and more AI (Artificial Intelligence) engines to detect several attack types. However, in order to be efficient in both learning and inference phases, such systems must include hardware coprocessors to improve AI-related computations. In this PhD thesis, we would like to explore the capabilities of RISC-V based processors in this context. RISC-V is an open-source ISA (Instruction Set Architecture) than can be easily extended. The main goal of this thesis is to propose RISC-V extensions for an IDS embedded into collaborative and heterogeneous unmanned vehicles (submarine, marine, or aerial): it must detect abnormal behaviors and must be efficient in terms of power consumption, area and runtime overheads. Furthermore, coprocessors developed in this thesis should not introduce security breaches into the system. Finally, a proof-of-concept should be developed to demonstrate the efficiency of algorithms and hardware implementations compared to software solutions.
|
Titre |
no
RISC-V Embedded AI for IDS Applications
|
Auteur(s) |
Pierre Garreau
1, 2, 3
, Pascal Cotret
1, 4
, Julien Francq
5
, Jean-Christophe Cexus
6, 4
, Loïc Lagadec
1, 4
1
Lab-STICC_ARCAD -
Equipe Hardware ARchitectures and CAD tools
( 1067624 )
- France
2
EN -
Ecole Navale
( 300396 )
- BCRM Brest, CC600, 29240 Brest CEDEX 9
- France
3
Chaire de Cyber Défense des Systèmes Navals [Brest]
( 471457 )
- École navale
CC 600
29240 BREST CEDEX 9
- France
4
ENSTA Bretagne -
École Nationale Supérieure de Techniques Avancées Bretagne
( 301846 )
- 2 rue François Verny, 29806 Brest cedex 9
- France
5
Naval Group
( 553134 )
- France
6
Lab-STICC_PIM -
Equipe PIM
( 1067613 )
- France
|
Langue du document |
Anglais
|
Titre du congrès |
RESSI 2024 : Rendez-vous de la Recherche et de l'Enseignement de la Sécurité des Systèmes d'Information
|
Date début congrès |
2024-05-15
|
Date fin congrès |
2024-05-17
|
Ville |
Eppe-Sauvage
|
Pays |
France
|
Actes |
Non
|
Date de publication |
2023-01-16
|
Vulgarisation |
Non
|
Comité de lecture |
Oui
|
Invité |
Non
|
Audience |
Nationale
|
URL du congrès ou éditeur |
https://ressi2024.sciencesconf.org/
|
Domaine(s) |
|
Financement |
|
Origine :
Fichiers produits par l'(les) auteur(s)
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