Previous theoretical and experimental works revealed the novel factors that Magnetic tunnel junction (MTJ) can be integrated into novel hybrid circuits except for memory applications. This paper exploits hybrid CMOS-MTJ circuit to diminish layout penalty of on-chip passive component in sigma-delta analog-to-digital converter (SD-ADC). Large poly resistance can be replaced by series connected MTJs with magneto-resistance. Simulation results show that MTJ based resistor-capacitor (RC) integrator can greatly reduce the resistance layout area by 94.52% comparing with 28-nm fully CMOS design. This novel design improves other ADC Figures of merit (FoM), including 0.06 bit Effective Numbers of Bits (ENOB) increment and stable performance under temperature variations. The design trade-off is 1.1 dB reduction of Signal-to-Noise Ratio (SNR).