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Communication Dans Un Congrès Année : 2020

3D RRAMs with Gate-All-Around Stacked Nanosheet Transistors for In-Memory-Computing

Résumé

This paper explores a novel 3D one transistor / one RRAM (1T1R) memory cube. The proposed architecture integrates HfO2-based OxRAM with select junctionless (JL) transistors based on low-voltage Gate-All-Around (GAA) stacked NanoSheet (NS) technology. A bitcell size of 23.9×F 2 /N is achieved ('N' being the number of stacked-NS) as well as a very high write and read parallelism. Extensive characterization of JL transistors and OxRAMs is performed to show their ability to be co-integrated inside a same 1T1R memory cell. Electrical characterization of 4kbits OxRAM arrays shows a large memory window (HRS/LRS=20) up to 10 4 cycles with a current compliance of 150µA, compatible with the performances of our JL transistors. Then, we experimentally demonstrate scouting logic operations capability with 2 operands, which should be extended to 4 operands thanks to an original two cells/bit "double coding" scheme assessed by SPICE simulations. Finally, we evidenced that this computing scheme is 2 times more energy efficient than a write-verify approach. I. INTRODUCTION
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Dates et versions

hal-04442669 , version 1 (06-02-2024)

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S. Barraud, M. Ezzadeen, D. Bosch, T. Dubreuil, N. Castellani, et al.. 3D RRAMs with Gate-All-Around Stacked Nanosheet Transistors for In-Memory-Computing. 2020 IEEE International Electron Devices Meeting (IEDM), Dec 2020, San Francisco, France. pp.29.5.1-29.5.4, ⟨10.1109/IEDM13553.2020.9371982⟩. ⟨hal-04442669⟩
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